Texas Instruments Corporation

Shannon A Wichman

Qadeer Ahmad Qureshi

John H Cornish

Weiyuen Kau

Tuan Q Dao

Uming U Ko

Naoki Hayashi

An electronic system ( ) includes a first integrated circuit (IC) ( ) having a card system management interrupt (SMI) output pin (CRDSMI&num;) and interrupt pins (IRQ ), and a logic circuit ( ) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate ( ) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate ( ) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN). A second integrated circuit ( ) has a system management interrupt (SMI&num;) output pin and SMI circuitry ( ) including a SMI register ( ) connected to events sources eligible for SMI response including the card SMI output of the first integrated circuit. This second IC ( ) further has a mask SMI register ( ) connected to the SMI register ( ) to select particular ones of the events sources for SMI response. A logic circuit ( ) is fed by the SMI register ( ) for combining the selected events sources to supply an internal SMI output (SMIOUT). Other circuits, systems and methods are also disclosed.

System management mode circuits, systems and methods

An electronic system (100) includes a first integrated circuit (IC) (112) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ3-5), and a logic circuit (1620, 1630) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate (2672) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate (2672) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN). A second integrated circuit (110) has a system management interrupt (SMI#) output pin and SMI circuitry (2370) including a SMI register (2610) connected to events sources eligible for SMI response including the card SMI output of the first integrated circuit. This second IC (110) further has a mask SMI register (2620) connected to the SMI register (2610) to select particular ones of the events sources for SMI response. A logic circuit (2634, 2638) is fed by the SMI register (2610) for combining the selected events sources to supply an internal SMI output (SMIOUT). Other circuits, systems and methods are also disclosed.

Method and apparatus for handling system management interrupts (SMI) as

A computer system including an arrangement for programmably assigning interrupts to a larger set of interrupt channels. The computer system includes a microprocessing unit ('MPU' 102), a peripheral processing unit ('PPU' 110) that communicates with the MPU and a peripheral control unit ('PCU' 112) capable of communicating with the PPU and with at least one associated peripheral device. The PCU has associated therewith a first number, m, of interrupts for signalling to the MPU. The MPU has a second number, n, of interrupt channels over which interrupts are communicable to said MPU. A first register (IN1616) is provided in the PCU for storing a routing value representing the assignment of the m interrupts of the PCU to a selected subset of m channels of the n interrupt channels. A second register (IN1222) is provided in the PPU for storing the routing value. A number, m, connections are provided between the PCU and the PPU for transmitting the m interrupts from the PCU to the PPU. Finally, a logic unit (3820, 3830, 914) is provided that is responsive to the receipt of an interrupt on one of the m connections and to the stored routing value in the second register for communicating an interrupt to the MPU and for identifying to the MPU the m selected interrupt channels to which the communicated interrupt is assigned. Other devices, systems and methods are also disclosed.

Interrupt routing circuits, systems and methods

A microprocessor (5) having an on-chip floating point unit (31) is disclosed. According to the disclosed embodiments, the floating-point unit (31) is arranged in pipelined fashion, and permits out-of-order execution of instructions in the event that an instruction generates an exception, such as an underflow condition. Writeback queue control circuitry (70) is provided, which includes a writeback queue buffer (74) and a multiplexer (72). The multiplexer (72) is under the control of writeback queue control logic (75), and selects either the state of the writeback bus (WB) or the contents of the writeback queue buffer (74) for application to router circuitry (54), and thus writeback to a register file (39). Upon detection of an exception, the state of the writeback bus (WB) is forwarded to the execution units (56, 58, 60) for exception handling according to microcode, with a portion of the floating-point pipeline being flushed. Other instructions may execute, however, with their results stored in writeback queue buffer (74) until completion of the reformatting of the result having the exception. The contents of the writeback queue buffer (74) may be forwarded to the router circuitry (54) for writeback, and the floating-point status word (FSW) updated, in program order. Any of the results stored in the writeback queue buffer (74) that cause an exception may similarly be handled by the microcode sequence.

Microprocessor with pipeline status integrity logic for handling

A microprocessor (5) having a floating-point unit (31) with internal microcode control therein is disclosed. The microcode control is effected by a microsequencer (47) having a microcode ROM (68) and control circuitry (80) therein. A scheduler circuit (50) forwards status and condition information, such as results from floating-point operations received on buses (REG, RES, FS, X1) from elsewhere in the microprocessor (5), to a condition circuit (76; 76') in the microsequencer (47). The condition circuit (76; 76') includes a multiplexer (80) receiving each of the status values (STAT0 through STATn), along with a loop counter (81) and a programmable comparator (82). Microinstructions (.mu.WORD) accessed from the microcode ROM (68) include a select field (SEL), for controlling the multiplexer (80) to select one of the status values (STAT0 through STATn) or the contents of the counter (81) for comparison, an immediate field (IMMED) applied to the comparator (82) to supply a value against which the selected status value (STAT0 through STATn) or counter value is to be compared, and a type field (TYP) for selecting the type of comparison to be performed by the comparator (82). According to an alternative embodiment of the invention, a mask field (MASK) is applied to the output of the multiplexer (80) and to the immediate field (IMMED), so that the comparison is made only relative to selected bits therein. Microprogram control is then made in response to the result of the comparison made in the condition circuitry (76).

Microprocessor with dynamically controllable microcontroller condition

A peripheral controller device (14) controlling at least a first peripheral device (16) attached thereto, the controller device including a programmable and selectable buffer memory for utilization with a first type and a second type of write instruction for writing data to first type (24) and a second type (26), respectively, of memory in the peripheral device (16). The peripheral controller device includes an n deep buffer memory (36), where n is an integer greater than one, for buffering the write instructions. A user may programmably indicate whether only the first type of write instruction is to be buffered or both types of instructions are to be buffered. Responsive to such programming, write instructions are examined to determine if they are of the first type or the second type. Depending on the programming, write instructions of the second type are routed to the buffer or are routed by bypassing the buffer memory.

Buffer memory for I/O writes programmable selective

Integrated circuit design for handling of system management interrupts

A bus interface timing unit responsive to a system clock signal having a frequency that is selectable among a plurality of frequencies. The bus interface timing unit provides timing signals to a bus interface unit that performs functions involving control signals having predetermined timing requirements, such timing requirements being substantially independent of the frequency of the system clock signal. The bus interface timing unit includes a signal generator (20) which is responsive to the system clock signal, and which generates the control signals. These control signals include at least one event signal controlling a time duration in which a predetermined event occurs. Also included is a control unit (10), responsive to a signal representative of the selected frequency of the system clock signal, that controls the signal generator such that the event signal timing is generated in accordance with the predetermined requirements the selected frequencies.

Frequency independent PCMCIA control signal timing

A phase locked loop circuit 11 includes a phase detection circuit 12, a means for phase adjustment, and a recovery circuit 18. The phase detection circuit 12 monitors the phase relationship between two signals and communicates the phase relationship to the phase adjustment means. The phase adjustment means provides appropriate delay to one of the signals to synchronize the two signals. The recover circuit 18 monitors the phase adjustment means for synchronization failures and provides appropriate notice to the phase adjustment means. The phase locked loop circuit 11 provides improved phase jitter resolution through the phase adjustment means. The circuit provides failure identification and correction through the recovery circuit resulting in improved phase locked loop circuit performance and reliability.

Growing community of inventors

Dallas, TX, United States of America

Shannon A Wichman