Intel Corporation

Shanker R Nagesh

Samantha J Edirisooriya

Pankaj Kumar

Blaine Monson

K L Siva Prasad Gadey N V

Ashok Jagannathan

A method is described. The method includes maintaining a synchronized count value in each of a plurality of logic chips within a same package. The method includes comparing the count value against a same looked for count value in each of the plurality of logic chips. The method includes each of the plurality of logic chips recording in its respective local memory at least some of its state information in response to each of the plurality of logic chips recognizing within a same cycle that the count value has reached the same looked for count value.

Debugging architecture for system in package composed of multiple semiconductor chips

In one embodiment, an apparatus comprises a processor core and a power control unit. The power control unit is to identify the occurrence of a power loss from a primary power source, instruct the I/O controller to block further write requests from the one or more I/O devices and to send at least one pending write request stored by the I/O controller to the memory controller, and instruct the memory controller to complete at least one pending write request stored by the memory controller and to cause the memory to be placed into a self-refresh mode.

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Bengaluru, India

Shanker R Nagesh