Texas Instruments Corporation

Shankaranarayana Karantha

Chakravarthy Srinivasan

Tonmoy Shingal

Srikanth Manian

Jagdish Chand Goyal

Srinivas Theertham

Peeyoosh Nitin Mirajkar

Ashwin Ravisankar

Frequency synthesis is based on phase synchronizing PLL output across REFERENCE and VCO clock domains (including outputs for multiple PLLs), based on an input (REF-Domain) SYNC signal (phase timing reference). A frequency synthesizer includes a VCO to generate VCO_clk and a PLL output circuit, such as a channel divider, to generate PLL_OUT based on VCO_clk (in the VCO-Domain). The VCO loop includes a PD to phase compare an input PD_clock based on REF_CLK, and a VCO feedback signal based on divided VCO_clk (NDIV_out). SYNC alignment circuitry generates a SYNC alignment signal based on SYNC, PD_clk, and NDIV_out (REF-Domain), which is used to synchronize the PLL output circuit and PLL_OUT to SYNC. If a reference divider generates PD_clk, the SYNC alignment circuitry generates a reset to SYNC-align the reference divider. If the VCO loop uses fractional divide, the SYNC alignment circuitry resets the fractional modulator to a known sequence.

Phase syncronizing PLL output across reference and VCO clock domains

A wireless communications device has two or more multiple port memory units operable to perform encryption/decryption shuffling and processing. Other circuits and methods of manufacture and operation are also disclosed.

Processes, circuits, devices, and systems for concurrent dual memory access in encryption and decryption

A wireless communications device () has a digital section () and a radio frequency section (). The digital section () does setup and execution on a set of data in at least first and second threads concurrently in a series of overlapping iterations by dividing the set of data into at least two different subsets and concurrently reading and writing in both subsets. A state machine () is shared by the setup and execution iterations. Two or more memory units () segregate the set of data, the predetermined size of the set of data in the memories () combined comprehending the total number of addresses occupied by the set of data utilized in operation of circuitry (). Dirty bits () are accessible at addresses corresponding to addresses in the memory. A selector circuit () has a selector output selectively coupled to an address line, and to a data line. The selector circuit () responds to a state on a dirty bit line (db) to couple data bits related to the address bits themselves from the address line () to the selector output (). Other circuits and methods of manufacture and operation are also disclosed.

Process, circuits, devices, and systems for encryption and decryption and other purposes, and process making

Processes, circuits, devices, and systems for encryption and decryption and other purposes, and processes of making

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Shankaranarayana Karantha