Hewlett-packard Development Company, L.P.

Rgb Networks, Inc.

Shankar Venkataraman

Padmanabha I Venkitakrishnan

Stuart Siu

Paul S Keltcher

Joseph Ku

Hain-Ching Liu

Yuval Fisher

Stephen Richardson

Gary Vondran

Dan R Hunt

Hsiang-Yun Alex Huang

A video stream is transcoded to provide a plurality of primary profiles. Individual frames of the video stream have a Presentation Time Stamp (PTS). A PTS is used as a token to identify particular frames to be encoded as Instantaneous Decoder Refresh (IDR) frames in each profile. An IDR frame period is determined, indicative of a desired number of video frames between two IDR frames. An IDR frame is inserted into each profile every IDR frame period. The IDR frames of each profile are aligned with the same IDR frames of the other profiles. The PTS of each IDR frame in each profile is monitored. Upon determining that a PTS is out of alignment, the next PTS of the affected profile is aligned with the corresponding PTS of remaining profiles. Backup transcoders produce backup profiles that are maintained in alignment with each other and with the primary profiles.

Method and apparatus for aligning IDR frames in transcoded multi-bitrate video streams

A streamlined cache coherency protocol system and method for a multiple processor single chip device. There are three primary memory unit (e.g., a cache line) states (modified, shared, and invalid) and three intermediate memory unit pending states. The pending states are used by the present invention to prevent race conditions that may develop during the completion of a transaction. The pending states 'lock out' the memory unit (e.g., prevent access by other agents to a cache line) whose state is in transition between two primary states, thus ensuring coherency protocol correctness. Transitions between states are governed by a series of request and reply or acknowledgment messages. The memory unit is placed in a pending state while appropriate measures are taken to ensure access takes place at an appropriate time. For example, a modification occurs only when other agents can not access the particular memory unit (e.g., a cache line).

Streamlined cache coherency protocol system and method for a multiple processor single chip device

Multiple processors are mounted on a single die. The die is connected to a memory storing multiple operating systems or images of multiple operating systems. Each of the processors or a group of one or more of the processors is operable to execute a distinct one of the multiple operating systems. Therefore, resources for a single operating system may be dedicated to one processor or a group of processors. Consequently, a large number of processors mounted on a single die can operate efficiently.

Chip multiprocessor with multiple operating systems

Growing community of inventors

Cupertino, CA, United States of America

Shankar Venkataraman