Microsoft Technology Licensing, LLC

Shankar S Narayan

Ryan Scott Haraden

Derek E Gladding

Nitin Garegrat

Zahid S Hussain

George Easton Scott, Iii

Sujatha Santhanaraman

Jayadev Velagandula

George Easton Iii Scott

A command queue is configured to receive a command from a software application. A configuration storage is configured to store a plurality of configurations. A matrix multiplication unit is configured to perform matrix multiplication operations. Memory is configured to store matrices. A control engine is configured to retrieve the command from the command queue; retrieve a configuration from the configuration storage based on the command; generate, based on the command and the configuration, instructions for the matrix multiplication unit to perform a set of matrix multiplication operations on first and second matrices stored in the memory; send the instructions to the matrix multiplication unit to configure the matrix multiplication unit to output results of the set of matrix multiplication operations; and store the results in a third matrix in the memory.

Performing tensor operations using a programmable control engine

Each processor of the SIMD array performs the computations for a respective neuron of a neural network. As part of this computation, each processor of the SIMD array multiplies an input to a weight and accumulates the result for its assigned neuron each (MAC) instruction cycle. A table in a first memory is used to store which input is fed to each processor of the SIMD array. A crossbar is used to route a specific input to each processor each MAC cycle. A second memory is used to provide the appropriate weight to each processor that corresponds the input being routed to that processor.

Neural network processor

An integrated circuit includes a pipeline of compare logic stages. The pipeline, at successive pipeline stages, determines whether each of a set of input symbols meets a corresponding programmable criteria. The compare logic stages each compare the set of input symbols to a respective programmable value. The compare logic stages also each provide, to a respective successive compare logic stage, a corresponding plurality of indicators of whether respective ones of the set of input symbols met the corresponding programmable criteria for that compare logic stage. The corresponding programmable criteria are configurable to be based at least in part on the corresponding plurality of indicators from a respective previous compare logic stage.

Highspeed/low power symbol compare

Embodiments of the present disclosure include systems and methods for storing tensors in memory based on depth. In some embodiments, for each of a plurality of sets of elements in a three-dimensional (3D) matrix, a position is determined along a height axis and width axis of the 3D matrix. At the determined position, a set of elements are identified along a depth axis of the 3D matrix. The set of elements are stored in a contiguous block of memory.

Storing tensors in memory based on depth

Various embodiments relating to selecting a motion vector in a hardware encoder are disclosed. In one example, a plurality of candidate predicted motion vectors are selected, and a plurality of motion searches are performed in an image region surrounding each candidate predicted motion vector to produce a plurality of resulting motion vectors, wherein each resulting motion vector has an initial cost score determined using a corresponding candidate predicted motion vector. After an actual predicted motion vector becomes available, the initial cost score of each resulting motion vector is re-scored using the actual predicted motion vector to produce an updated cost score, and video data is encoded using a motion vector selected from the plurality of resulting motion vectors based on the updated cost score of that motion vector.

Growing community of inventors

Saratoga, CA, United States of America

Shankar S Narayan