Intel Corporation

Sk Hynix Nand Product Solutions Corp.

Intel Ndtm US LLC

Shankar Natarajan

Suresh Nagarajan

Sriram Natarajan

Arun Sitaram Athreya

Yihua Zhang

Romesh B Trivedi

Arun Athreya

Aliasgar S Madraswala

Shivashekar Muralishankar

Rohit Sudhir Shenoy

Ramkarthik Ganesan

Ning Wu

Wayne D Tran

Parth Donga

Mariusz Dolny

Hinesh K Shah

Bartosz Kot

Richard M Fastow

Chang Wan Ha

Khaled Hasnat

Anoop Mukker

Shafqat Ahmed

Chuan Lin

Jason R Cox

Naveen Vittal Prabhu

Sahar Khalili

Jason B Akers

Michal Mamczyński

Grzegorz Kowalczyk

Michał Mamczyński

Orapin Yoder

Charles B Foster

Venkata S Surampudi

Chee Law

Scott Crippin

A system and related method, including system memory with a source memory block and a destination memory block each of a memory block size, a first volatile memory and a second volatile memory, each of a volatile memory size. The system includes processing circuitry to receive a garbage collection request associated with the destination memory block. The processing circuitry then determines whether the memory block size is greater than the volatile memory size and pauses data change operations but allows for passive operations to continue. While data change operations are paused the processing circuitry loads a first portion of data of the source memory block to the first volatile memory and a second portion of the data to the second volatile memory. The processing circuitry writes each portion of data from the volatile memory to the destination memory block to complete garbage collection and unpauses the data change operations.

System and methods for DRAM-less garbage collection with improved performance

A system and related method, the system including control circuitry and memory with a first memory block of a first memory density and a second memory block of a second memory density which is greater than the first memory density. Control circuitry, which is communicatively coupled to the memory, is configured to determine to transfer data from the first memory block to the second memory block, generate parity data based on the data and cause to store the parity data at a parity address corresponding to an available portion of the first memory block. Control circuitry is further to cause to update a look-up table with the parity data address and cause to copy the data from the first memory block to the second memory block.

Flexible raid parity application for memory management

A system and related method, including memory and processing circuitry, which is to write data of a data stream. The memory includes a first memory portion of a first density and a second memory portion of a second density. The processing circuitry receives a write request. The processing circuitry is then to select to write the data to the first memory portion based on a characteristic of the data stream, wherein both the first memory portion and the second memory portion are available to be written to, and the processing circuitry then causes the data to be written to the first memory portion. The processing circuitry may select to write the data to the first memory portion based on a size of the data stream and/or based on a bandwidth of writing data of the data stream to the memory.

Host bandwidth optimized data stream memory writes

A system and related method, including storage circuitry and a control circuitry, which while executing a storage device driver, is to receive at least one instruction of a stream of instructions for the storage device. The control circuitry determines that a hardware buffer of the storage device is storing less than two instructions. In response to the determination that the hardware buffer of the storage device is storing less than two instructions, the control circuitry accesses data associated with an address of the memory of the storage device, wherein the address is predicted based on analysis of the stream of instructions and causes to be stored the data in a buffer of a plurality of buffers. The control circuitry executes an instruction of the stream of instructions using at least the data stored in the buffer.

Methods and systems for software based prefetching for low buffer depth sequential read traffic

This application is directed to data protection in a memory system of an electronic device. The memory system has a first memory block and a second memory block, and each memory block includes one or more respective memory dies. Each memory die of the second memory block is distinct from the one or more respective memory dies of the first memory block. The electronic device stores user data including a plurality of user data items in the first memory block and integrity data including a plurality of integrity data items in the second memory block. Each of the plurality of user data items is configured to be validated based on a respective one of the plurality of integrity data items. The electronic device invalidates the integrity data in the second memory block, and reads the user data from the first memory block independently of the integrity data.

Controlling memory overhead for storing integrity data in solid state drives

An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.

Persistent data structure to track and manage SSD defects

In one example, reads in a NAND memory device are tracked for sub-groups. When the number of reads to a sub-group meets a threshold, the data at the wordline on which the threshold was met is moved along with the data at neighboring wordlines to an SLC block without moving the entire block. The performance impact and write amplification impact of read disturb mitigation can be significantly reduced while maintaining some data continuity.

Techniques for preventing read disturb in NAND memory

A solid state drive with a Logical To Physical (L2P) indirection table stored in a persistent memory is provided. The L2P indirection table has a plurality of entries, each entry to store a physical block address in the block addressable memory assigned to a logical block address. The solid state drive including solid state drive controller circuitry communicatively coupled to the persistent memory and the block addressable memory. The solid state drive controller circuitry including a volatile memory to store a logical to physical address indirection table cache and circuitry to monitor the logical to physical address indirection table cache and to write dirty logical to physical entries in the logical to physical address indirection table cache to the logical to physical address indirection table in the persistent memory.

Logical to physical address indirection table in a persistent memory in a solid state drive

Dirty Logical-to-Physical (L2P) entries in an L2P indirection table stored in a host volatile memory buffer are flushed to non-volatile memory in the solid state drive through the use of a write-back mode based on flush checkpoints. The use of write-back mode to flush dirty entries in the L2P indirection table to non-volatile memory in the solid state drive based on flush checkpoints results in an increase in the write bandwidth of the solid state drive.

Host managed buffer to store a logical-to physical address table for a solid state drive

Programming a multilevel cell (MLC) nonvolatile (NV) media can be performed with internal buffer reuse to reduce the need for external buffering. The internal buffer is on the same die as the NV media to be programmed, along with a volatile memory to store data to program. The internal buffer is to read and program data for the NV media. Programming of the NV media includes staging first partial pages in the buffer for program, reading second partial pages from the NV media to the volatile memory, storing second partial pages in the buffer, and programming the NV media with the first partial pages and the second partial pages.

Utilizing NAND buffer for DRAM-less multilevel cell programming

Techniques for preventing read disturb in NAND memory devices are described. In one example, reads are tracked for sub-groups. When the number of reads to a sub-group meets a threshold, the data at the wordline on which the threshold was met is moved along with the data at neighboring wordlines to an SLC block without moving the entire block. The performance impact and write amplification impact of read disturb mitigation can be significantly reduced while maintaining some data continuity.

A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.

Reducing power consumption in nonvolatile memory due to standby leakage current

A nonvolatile (NV) memory device includes an NV storage media and a storage controller to control access to the NV storage media. In response to a host read request, the storage controller can determine if the NV storage media is in a stable Vt (threshold voltage) state. If the NV storage media is in a stable Vt state, the storage controller can perform a reset read operation prior to servicing the host read request. A reset read is a read operation that does not produce data to send back to the host. The reset read operation is a dummy read that puts the NV storage media into a transient Vt state, which has lower risk of read disturb.

System approach to reduce stable threshold voltage (Vt) read disturb degradation

Write performance of a block-based multi-level cell non-volatile memory is increased through the use of an internal copy of blocks with a high validity. Write (program) performance for sequential workloads is increased by moving the data in blocks with a high validity within a NAND device directly from the portion of the NAND device configured as single level cell NAND to the portion of the NAND device configured as multi-level cell NAND.

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Folsom, CA, United States of America

Shankar Natarajan