Nvidia Corporation

Shankar Moni

Pankaj Chaurasia

Atul Garg

Ignatius B Tjandrasuwita

Iole Moccagatta

Dipankar Talukdar

Sandeep Shyamsukha

Christopher L Mills

Harikrishna Madadi Reddy

Derek E Pappas

Matthew Raymond Longnecker

A video processor is described, which is useful for implementing a forward transform process, in compliance with the H.264 standard. The video processor includes an input, for receiving a block of image data. The image data is loaded into an internal register. In response to receiving a SIMD instruction, a multiplier, which incorporates the H.264 forward transform matrix in its associated hardware, processes the block of image data, and writes the resulting partially transformed pixel data back to the internal register, transposing the data during the process.

Forward and inverse transformation of data for video compression

A video processor is described, which is useful for implementing a Hadamard transform process, in compliance with the H.264 standard. The video processor includes an input, for receiving a block of image data. The image data is loaded into an internal register. In response to receiving a SIMD instruction, a multiplier, which incorporates the H.264 Hadamard transform matrix in its associated hardware, processes the block of image data, and writes the resulting partially transformed pixel data back to the internal register, transposing the data during the process.

Hadamard transformation of data for video compression

A video processor is described, which is useful for implementing a quantization process, in compliance with the H.264 standard. The video processor includes an input, for receiving a block of image data. The image data is loaded into an internal register. In response to receiving a SIMD instruction, a quantizer, which incorporates the quantization lookup tables associated with the H.264 standard in its associated hardware, makes necessary high-level quantization decisions. In response to receiving another SIMD instruction, the quantizer uses those high-level quantization decisions to retrieve specific values from the quantization lookup tables.

Forward and inverse quantization of data for video compression

Described are methods and systems for processing data. A motion estimator uses a block of an input frame of video data and a block of a reference frame of video data to generate motion vectors according to a first encoding scheme. A motion compensator produces half pel motion vectors from the motion vectors according to a second encoding scheme that is different from the first encoding scheme.

Adapting one type of encoder to another type of encoder

The present invention includes a method and system for encoding video data by accessing a picture to be encoded, wherein the picture comprises a plurality of macro-blocks. A plurality of programmable counters are associated with each macro-block to be encoded. A counter associated with a macro-block of the plurality of macro-blocks is accessed and a value of the counter is determined. The method further includes determining whether to encode the macro-block as an Intra or non-Intra based on the value of the counter. If the macro-block is encoded as Intra, its counter is reset. If the macro-block is encoded as non-Intra, its counter value is updated. The counter value may be reset with a random number. Counters can be programmed such that a region of interest is defined for updating associated macro-blocks with greater frequency.

System and method for intra refresh implementation

System and method for intra refresh implementation with pseudo random number generation

Several different approaches to performing the modulus operation are presented. In one, a method of performing the modulus operation upon a dividend and a divisor within a limited range is discussed. The method involves storing a reference value, receiving a dividend value, and calculating a number of derived inputs. Each of the derived inputs corresponds to the dividend value minus the reference value, and is then further modified by a multiple of the divisor. Using the divisor to select between these derived inputs provides the answer.

Single-cycle modulus operation

A bitstream generator is described, for placing variable length coding (VLC) data into a fixed width data stream. The bitstream generator includes an input for receiving VLC data; the VLC data may be separated into a value component, and a length component. The bitstream generator also includes an output buffer, a memory module, for storing the VLC data before sending. The bitstream generator also incorporates a backup buffer, which is used to store any overflow data which does not fit in the output buffer. A comparator is used, to determine how much of the VLC data will fit in the output buffer. Any portion of the VLC data which does not fit in the output buffer is stored in the backup buffer.

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Bengaluru, India

Shankar Moni