International Business Machines Corporation

Shankar Kalyanasundaram

Rolf Sautter

Juergen Pille

Alexander Fritsch

Ananth Nag Raja Darla

Tobias Werner

Michael B Kugel

Amira Rozenfeld

Werner Juchmes

Rajesh Veerabhadraiah

Amit Bipinbhai Patel

Krishnan Mohan

A method of designing an integrated circuit (IC) chip is discloses. The method includes designing a higher level comprising a plurality of outputs configured to be connected to inputs in a previously-designed macro level, wherein each input in the macro level includes a configurable filler cell. The method also includes calculating if each input includes an antenna violation based on the higher level and the macro level, and configuring each of the filler cells, wherein each filler cell associated with an antenna violation is configured as an antenna diode.

Filler cells for integrated circuit design

An integrated circuit includes at least one first area including logic circuitry. The logic circuitry includes library blocks selected from a logic circuit library. A first one of the library blocks is provided with at least two symmetry mirror edges perpendicular to a height of the library blocks. Two adjacent ones of the library blocks are joined at a common symmetry mirror edge.

Integrated circuit including logic circuitry

Techniques for generating a layout of a multi-port memory cell are provided. A specification describing at least on port within a memory cell is defined. A base memory cell including at least one extension point is modeled. A port that interfaces with the base memory cell is identified from the specification. An electrical interface between the identified port and an extension point of the base memory cell is modeled. In some embodiments, a design bucket is selected from among a predefined set of design buckets based on a count of ports within the memory cell, as described by the specification. Each design bucket corresponding to a respective layout template including the base memory cell and a respective maximum count of ports. Each electrical interface including a port described in the specification of the memory cell is modeled based on the selected design bucket and the respective layout template.

Layout of a memory cell of an integrated circuit

A memory apparatus includes a content addressable memory, CAM, cell block including CAM cells and a random access memory (RAM), cell block including RAM cells. A geometric footprint of each of the CAM cells has a side bigger than a side of a geometric footprint of each of the RAM cells, where the sides of the CAM cells and the RAM cells are parallel to each other. The apparatus is configured to translate an input keyword at an input of the CAM cell block to an output word at an output of the RAM cell block when the keyword at the input of the CAM cell block is stored in the CAM cell block. The CAM cell block is split into a first part and a second part of the CAM cells.

Content addressable memory array comprising geometric footprint and RAM cell block located between two parts of a CAM cell block

Single ended bitline current sense amplifier for SRAM applications. The present disclosure relates to current sense read amplifier for use as a read amplifier in a memory arrangement of memory cell groups, wherein in each of the memory cell groups cells includes at least one read port connected to a read amplifier by a bitline, and wherein said read amplifiers are connected to a data output. The current sense read amplifier includes a voltage regulator to keep a bitline voltage at a constant voltage level below a power supply voltage and above a ground, a measurement circuit to detect a high current value and a low current value in a input signal, and a generator to generate a high voltage level output signal when the high current value input is detected and to generate a low voltage level output signal when the low current level value is detected.

Growing community of inventors

Bengaluru, India

Shankar Kalyanasundaram