Sandisk Technologies Inc.

Shankar Guhados

Feng Q Pan

Jun Wan

Bo Lei

Jun Wang

Jonathan Huynh

Sagar Magia

Sung-En Wang

Techniques are presented for determining current levels based on the behavior of a charge pump system while driving a load under regulation. While driving the load under regulation, the number of pump clocks during a set interval is counted. This can be compared to a reference that can be obtained, for example, from the numbers of cycles needed to drive a known load current over an interval of the duration. By comparing the counts, the amount of current being drawn by the load can be determined. This technique can be applied to determining leakage from circuit elements, such as word lines in a non-volatile memory.

Charge pump based over-sampling ADC for current detection

Techniques are presented for determining current levels based on the behavior of a charge pump system while driving a load under regulation. While driving the load under regulation, the number of pump clocks during a set interval is counted. This can be compared to a reference that can be obtained, for example, from the numbers of cycles needed to drive a known load current over an interval of the duration. By comparing the counts, the amount of current being drawn by the load can be determined. This technique can be applied to determining leakage from circuit elements, such as word lines in a non-volatile memory. The accuracy and level of resolution can be further increased through use of sigma delta noise shaping.

Sigma delta over-sampling charge pump analog-to-digital converter

A right-half plane (RHP) zero (RHZ) compensation scheme to improve the stability of the operational amplifier. A resistance Ris implemented by a transistor. This transistor tracks process variations of the transistor drive by the op-amp to achieve better stability without requiring a bandwidth reduction. As a current source is not available to bias this transistor, a local bias circuit is used to provide this.

Compensation scheme to improve the stability of the operational amplifiers

Techniques are presented to improve the performance, accuracy and power consumption of on-chip voltage biasing and transmission for highly loaded RC networks (such as wordlines or bitlines in NAND or 3D memory arrays) that are otherwise limited by the physics of RC time constant. When transitioning the near-end voltage of the network, an under-drive or over-drive level is applied, combined with feedback control to estimate when the far-end voltage approaches the desired level.

High speed signaling techniques to improve performance of integrated circuits

Techniques are presented for improving the wake-up response of voltage regulation circuits. A first set of techniques relate to the inputs an op-amp in a regulation circuit. In regulated operation, one input receives feedback from the regulator's output. Instead, during reset, after resetting the op-amp's output node to the supply level, this input of op-amp is instead connected to ground in order to increase the amount of tail current through the op-amp in order to more quickly bring down the op-amp's output node. A detection circuit is introduced to determine when the op-amp's input is reconnected to receive feedback. In a complementary sets of techniques, when the circuit on which the regulator is formed receives an enable signal and the output of the regulator will be needed for an operation, and when the regulator is not yet back at operating levels, its supply is temporarily shorted to the supply level.

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Fremont, CA, United States of America

Shankar Guhados