Intel Corporation

Other

Shankar Ganapathysubramanian

Aleksandar Aleksov

Sujit Sharan

Leonel R Arana

Jorge A Sanchez

Vladimir Noveski

Nitin A Deshpande

Eric Jin Li

Mitul Bharat Modi

Sandeep B Sane

Richard J Harries

Vijay Wakharkar

Nirupama Chakrapani

Sankara J Subramanian

Sudarshan V Rangaraj

Jiraporn Seangatith

Poh Chieh Benny Poon

Dingying David Xu

Nisha Ananthakrishnan

Mohit Mamodia

Gregory S Constable

Janet Feng

Wen Feng

Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate.

Die warpage control for thin die assembly

A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.

Package substrate and die spacer layers having a ceramic backbone

Die warpage is controlled for the assembly of thin dies. In one example, a device having a substrate on a back side and components in front side layers is formed. A backside layer is formed over the substrate, the layer resisting warpage of the device when the device is heated. The device is attached to a substrate by heating.

A treatment for a microelectronic device comprises a dicing tape () and a polymer composite film () having a pigment or other colorant added thereto and, in some embodiments, a pre-cure glass transition temperature greater than 50&#xb0; Celsius. The film can comprise multiple layers, with one layer being tacky and the other layer non-tacky at a given temperature.

Treatment for a microelectronic device and method of resisting damage to a microelectronic device using same

Methods for fabricating a layer or layers for use in package substrates and die spacers are described. In one implementation the layer or layers are fabricated to include a plurality of ceramic wells lying within a plane and separated by metallic via with recesses within the ceramic wells being occupied by a dielectric filler material.

Method for fabricating package substrate and die spacer layers having a ceramic backbone

A microelectronic package is provided. The microelectronic package includes a semiconductor substrate and a die having a top surface and a bottom surface, wherein the bottom surface of the die is coupled to the semiconductor substrate. The microelectronic package also includes a nanomaterial layer disposed on the top surface of the die.

Microelectronic package with wear resistant coating

A linear coefficient of thermal expansion (CTE) mismatch between two materials, such as between a microelectronic die and a mounting substrate, may induce stress at the interface of the materials. The temperature changes present during the process of attaching a die to a mounting substrate can cause cracking and failure in the electrical connections used to connect the die and mounting substrate. A material with a CTE approximately matching the die CTE is introduced in the mounting substrate to reduce the stress and cracking at the electrical connections between the die and mounting substrate. Additionally, this material may comprise thin film capacitors useful for decoupling power supplies.

Embedded capacitors for reducing package cracking

A compliant structure for an electronic device comprises a substrate () composed of a first material () and a compliant zone () within the substrate. A plurality of solder joints () are located between, and form a connection between, the substrate and the electronic device (). The compliant zone reduces the degree of deformation experienced by the solder joints due to thermal mismatch loading between the substrate and the die during attachment of the die to the substrate (chip attach). This reduction in solder joint deformation reduces the likelihood that the solder joints will crack.

Compliant structure for an electronic device, method of manufacturing same, and system containing same

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Phoenix, AZ, United States of America

Shankar Ganapathysubramanian