Texas Instruments Corporation

Shanjen Pan

Sameer P Pendharkar

James Robert Todd

Pinghai Hao

Tsutomu Kubota

Allan T Mitchell

Xiaoju Wu

Weidong Tian

Zafar Imam

Jack G Qian

Larry B Anderson

Fan Chi Hou

Yvonne Patton

Alan T Mitchell

Jozef D Mitros

In an embodiment of the invention, a method of fabricating a floating-gate NMOSFET (n-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves as the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation.

N-channel erasable programmable non-volatile memory

In an embodiment of the invention, a method of fabricating a floating-gate PMOSFET (p-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves at the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation.

Electrically erasable programmable non-volatile memory

The present invention provides, in one embodiment, a transistor (). The transistor () comprises a doped semiconductor substrate () and a gate structure () over the semiconductor substrate (), the gate structure () having a gate corner (). The transistor () also includes a drain-extended well () surrounded by the doped semiconductor substrate (). The drain-extended well () has an opposite dopant type as the doped semiconductor substrate (). The drain-extended well () also has a low-doped region () between high-doped regions (), wherein an edge of the low-doped region () is substantially coincident with a perimeter () defined by the gate corner (). Other embodiments of the present invention include a method of manufacturing a transistor () and an integrated circuit ().

Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof

A semiconductor device () that includes a drain extended PMOS transistor (CT) is provided, as well as fabrication methods () therefore. In forming the PMOS transistor, a drain () of the transistor is formed over a region () of a p-type upper epitaxial layer (), where the region () of the p-type upper epitaxial layer () is sandwiched between a left P-WELL region () and a right P-WELL region () formed within the p-type upper epitaxial layer (). The p-type upper epitaxial layer () is formed over a semiconductor body () that has an n-buried layer () formed therein. This arrangement serves to increase the breakdown voltage (BVdss) of the drain extended PMOS transistor.

Drain extended PMOS transistor with increased breakdown voltage

Semiconductor devices and manufacturing methods therefor are disclosed, in which a drain-extended MOS transistor comprises a self-aligned floating region proximate one end of the transistor gate and doped with a first type dopant to reduce channel hot carrier degradation, as well as an oppositely doped first source/drain laterally spaced from the first end of the gate structure in a semiconductor body. The device may further comprise a resurf region doped to a lower concentration than the floating region to facilitate improved breakdown voltage performance. A method of fabricating a drain-extended MOS transistor in a semiconductor device is disclosed, comprising providing first dopants to a floating region in a semiconductor body, which is self-aligned with the first end of a gate structure, and providing second dopants to source/drains of the semiconductor body, wherein the first and second dopants are different.

Drain extended MOS devices with self-aligned floating region and fabrication methods therefor

Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer is formed over the device. A gate electrode layer is formed that serves as the gate electrode and a bottom capacitor plate. The gate electrode and the gate dielectric layer are patterned to form gate structures. Source and drain regions are formed within the well regions and the drain extension regions. A silicide blocking layer is formed that also serves as a capacitor dielectric. Field plates and a top capacitor plate are formed on the blocking layer.

Methods of fabricating high voltage devices

A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shallow region therein. The first dopant penetrates the substrate to a depth that is less than the LDD junction depth. A second dopant is implanted into the substrate beyond the LDD junction depth to form a source/drain region. The implantation of the second dopant overpowers a substantial portion of the first dopant to define a floating ring in the LDD region that mitigates channel hot carrier effects.

Reduction of channel hot carrier effects in transistor devices

A CMOS integrated circuit (A-B-C) includes both relatively low-power () and high-power () CMOS transistors on the same chip. A 20V, relatively high-power PMOS device () includes a heavily doped N-well drain region (). A 20V, relatively high-power NMOS device () includes heavily doped P-type buried layers () underneath the source () and drain regions () and spanning the gap between the P-well gate (F) and adjacent P-well isolation regions ().

Method and structure for a low voltage CMOS integrated circuit incorporating higher-voltage devices

The present invention provides, in one embodiment, a method of reducing 1/f noise in a metal oxide semiconductor (MOS) device (). The method comprises forming an oxide layer () on a silicon substrate () and depositing a polysilicon layer () on the oxide layer (). The method further includes implanting a fluorine dopant () into the polysilicon layer () at an implant dose of at least about 4&#xd7;10atoms/cm. The polysilicon layer () is thermally annealed such that a portion of the fluorine dopant () is diffused into the oxide layer () to thereby reduce a 1/f noise of the MOS device (). Other embodiments of the provide a MOS device () manufactured by the above-described method and a method of manufacturing an integrated circuit () that includes the above-described method.

Method for manufacturing a MOS transistor having reduced 1/f noise

Depletion drain-extended MOS transistor devices and fabrication methods for making the same are provided, in which a compensated channel region is provided with p and n type dopants to facilitate depletion operation at Vgs=0, and an adjust region is implanted in the substrate proximate the channel side end of the thick gate dielectric structure for improved breakdown voltage rating. The compensated channel region is formed by overlapping implants for an n-well and a p-well, and the adjust region is formed using a Vt adjust implant with a mask exposing the adjust region.

Depletion drain-extended MOS transistors and methods for making the same

Methods and apparatus are disclosed for fabricating thick and thin gate oxide transistors in a semiconductor device, wherein lightly doped source/drain regions for the thick gate oxide transistors are formed using a threshold voltage adjust implant, and lightly doped source/drain regions for the thin gate oxide transistors are formed using an LDD implant. The use of threshold voltage implantation to form the lightly doped source/drain regions for the thick gate oxide transistors allows lower dopant concentrations therein compared with the thin gate oxide transistors without the need for separate LDD implantation processing for transistors of different gate oxide thicknesses.

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Plano, TX, United States of America

Shanjen Pan