Semiconductor Components Industries, LLC

Shanghui Larry Tu

Gordon M Grivna

Zia Hossain

Mohammed Tanvir Quddus

Rajesh S Nair

Takeshi Ishiguro

Fumika Kuramae

John Michael Parsey, Jr

James Adams

Antonin Rozsypal

Ryuji Omi

In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening.

Edge seal for a semiconductor device and method therefor

In one embodiment, a Schottky diode is formed on a semiconductor substrate with other semiconductor devices and is also formed with a high breakdown voltage and a low forward resistance.

Schottky diode and method therefor

Edge seal for a semiconductor device

In one embodiment, a semiconductor device is formed having sub-surface charge compensation regions in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two opposite conductivity type semiconductor layers.

Method of forming a semiconductor device having sub-surface trench charge compensation regions

In one embodiment, a semiconductor structure comprises a multi-portioned guard ring that includes a first portion and a second portion formed in a region of semiconductor material. A conductive contact layer forms a first Schottky barrier with the region of semiconductor material. The conductive contact layer overlaps the second portion and forms a second Schottky barrier that has an opposite polarity to the first Schottky barrier. The conductive contact layer does not overlap the first portion, which forms a pn junction with the region of semiconductor material.

Schottky diode structure with multi-portioned guard ring and method of manufacture

In one embodiment, a method of forming a semiconductor device with trench charge compensation structures includes exposing the trench sidewalls to a reduced temperature hydrogen desorption process to enhance the formation of monocrystalline semiconductor layers.

Method of forming a semiconductor device having trench charge compensation regions

Semiconductor device having sub-surface trench charge compensation regions

In one embodiment, a high voltage semiconductor device is formed with a first dielectric layer and a charge stabilization layer comprising a flowable glass formed over the first dielectric layer.

Semiconductor device having field stabilization film and method

In one embodiment, a semiconductor device is formed having charge compensation trenches in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two opposite conductivity type semiconductor layers.

Semiconductor device having trench charge compensation regions and method

In one embodiment, a lateral FET cell is formed in a body of semiconductor material. The lateral FET cell includes a super junction structure formed in a drift region between a drain contact and a body region. The super junction structure includes a plurality of spaced apart filled trenches having doped regions of opposite or alternating conductivity types surrounding the trenches.

Semiconductor structure with improved on resistance and breakdown voltage performance

A lateral FET cell is formed in a body of semiconductor material. The lateral FET cell includes a super junction structure formed in a drift region between a drain contact and a body region. The super junction structure includes a plurality of spaced apart filled trenches bounding in part a multiplicity of striped doped regions having opposite or alternating conductivity types.

In one embodiment, a lateral FET cell is formed in a body of semiconductor material. The body of semiconductor material includes alternating layers of opposite conductivity type that extend between a trench drain region and a trench gate structure. The trench gate structure controls at least one sub-surface channel region. The body of semiconductor material provides sub-surface drift regions to reduce on resistance without increasing device area.

High voltage lateral FET structure with improved on resistance performance

In one embodiment, a lateral FET structure () is formed in a body of semiconductor material (). The structure () includes a plurality non-interdigitated drain regions () that are coupled together with a conductive layer (), and a plurality of source regions () that are coupled together with a different conductive layer (). One or more interlayer dielectrics () separate the two conductive layers (). The individual source regions () are absent small radius fingertip regions.

Growing community of inventors

Phoenix, AZ, United States of America

Shanghui Larry Tu