Taiwan Semiconductor Manufacturing Comp. Ltd.

Worldwide Semiconductor Manufacturing Corporation

Shang-Yun Hou

Shin-Puu Jeng

Chen-Hua Douglas Yu

Hsien-Pin Hu

Sung-Hui Huang

Chi-Hsi Wu

Wei-Cheng Wu

Kuan-Yu Huang

Kuo-Chiang Ting

Wen-Chih Chiou

Sao-Ling Chiu

Hao-Yi Tsai

Wen-Hsin Wei

Jing-Cheng Lin

Cheng-Chieh Hsieh

Ying-Ching Shih

Tzuan-Horng Liu

Hsing-Kuo Hsia

Kuo-Ching Hsu

Weiming Chris Chen

Ping-Kang Huang

Tu-Hao Yu

Hsien-Wei Chen

Der-Chyang Yeh

Tzu-Yu Wang

Tzu-Wei Chiu

Szu-Wei Lu

Chia-Hao Hsu

Wei-Ming Chen

Chia-Lun Tsai

Shih-Hsun Hsu

Li-Chung Kuo

Shih-Wen Huang

Chao-Hsiang Yang

Chun Hua Chang

Ting-Yu Yeh

Chung-Yu Lu

Kim Hong Chen

Chien-Yuan Huang

Po-Hao Tsai

Cheng-Lin Huang

Hsiao-Tsung Yen

Jiun Yi Wu

Chin-Fu Kao

Tsung-Yu Chen

Cheng-Hsien Hsieh

Wan-Yu Lee

Shu-Chia Hsu

Chih-Wei Wu

Yun-Han Lee

Bruce C S Chou

Chiung-Han Yeh

Yu-Wen Liu

Wen-Wei Shen

Chao-Wen Shih

Shuo-Mao Chen

Chen-Cheng Kuo

Tsung-Shu Lin

Ying-Hao Kuo

Wensen Hung

Li-Han Hsu

Yuan-Hung Liu

Szu-Po Huang

Shih Ting Lin

Hung-Jung Tu

Kuang-Wei Cheng

Tien-Yu Huang

Chi-Ming Huang

Chen-Shien Chen

An-Jhih Su

Hung-Yi Kuo

Jui-Pin Hung

Hsueh-Chung Chen

Chih-Hua Chen

Pei-Haw Tsao

Ming Hung Tseng

Jyh-Cherng Sheu

Chun-Jen Chen

Hung-Pin Chang

Yi-Jou Lin

Chen-Hua Lin

Yu-Jen Cheng

Mirng-Ji Lii

Ying-Ju Chen

Ching-Wen Hsiao

Han-Ping Pu

Chun-Hung Chen

Wei-Ting Lin

Hsin-Hui Lee

Szu Wei Lu

Sen-Bor Jan

Kai-Ming Ching

Shih-Ming Chen

Ming-Yen Chiu

Chung Yu Wang

Hsiu-Mei Yu

Kung-Chen Yeh

Francis Ko

Bai-Yao Lou

Hsien-Ju Tsou

A method includes bonding a first package component over a second package component, dispensing a first underfill between the first package component and the second package component, and bonding a third package component over the second package component. A second underfill is between the third package component and the second package component. The first underfill and the second underfill are different types of underfills.

Packages with multiple types of underfill and method forming the same

A package includes silicon waveguides on a first side of an oxide layer; photonic devices on the first side of the oxide layer, wherein the photonic devices are coupled to the silicon waveguides; redistribution structures over the first side of the oxide layer, wherein the redistribution structures are electrically connected to the photonic devices; a hybrid interconnect structure on a second side of the oxide layer, wherein the hybrid interconnect structure includes a stack of silicon nitride waveguides that are separated by dielectric layers; and through vias extending through the hybrid interconnect structure and the oxide layer, wherein the through vias make physical and electrical connection to the redistribution structures.

Photonic package and method of manufacture

A method includes attaching semiconductor devices to an interposer structure, attaching the interposer structure to a first carrier substrate, attaching integrated passive devices to the first carrier substrate, forming an encapsulant over the semiconductor devices and the integrated passive devices, debonding the first carrier substrate, attaching the encapsulant and the semiconductor devices to a second carrier substrate, forming a first redistribution structure on the encapsulant, the interposer structure, and the integrated passive devices, wherein the first redistribution structure contacts the interposer structure and the integrated passive devices, and forming external connectors on the first redistribution structure.

Integrated circuit package and method

A method of forming a semiconductor package includes: forming a first package component including a first and a second conductive bumps; forming a second package component including a third and a fourth conductive bumps, where dimensions of the first and second conductive bumps are less than dimensions of the third and fourth conductive bumps; and forming a first and a second joint structures to bond the second package component to the first package component. A first angle between an exposed sidewall of the first conductive bump and a tangent line at an end point of a boundary of the first joint structure on the sidewall of the first conductive bump is less than a second angle between an exposed sidewall of the second conductive bump and a tangent line at an end point of a boundary of the second joint structure on the sidewall of the second conductive bump.

Joint structure in semiconductor package and manufacturing method thereof

A package structure is provided. The package structure includes a semiconductor die structure over a substrate and bonding structures between the semiconductor die and the substrate. The package structure also includes multiple solder elements over the substrate. The solder elements together surround the semiconductor die structure, and each of the solder elements is longer than a side of the semiconductor die structure. The package structure further includes an underfill material surrounding the bonding structures. The underfill material is substantially confined within a region surrounded by the solder elements. The underfill material is in direct contact with at least one of the solder elements.

Package structure with underfill

A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

Encapsulated package including device dies connected via interconnect die

A semiconductor device includes a first electronic component, a second electronic component, a third electronic component, a plurality of first interconnection structures, and a plurality of second interconnection structures. The first electronic component is between the second and the third electronic components. The first interconnection structures are between the first and the second electronic components. Each first interconnection structures has a length along a first direction substantially parallel to a surface of the first electronic component, and a width along a second direction substantially parallel to the surface and substantially perpendicular to the first direction. The length is larger than the width. The second interconnection structures are between the second and the third electronic components, and electrically connected to the second and the third electronic components. A height of each second interconnection structure is different from a height of each first interconnection structure.

Semiconductor device

A semiconductor device includes a first Chip-On-Wafer (CoW) device having a first interposer and a first die attached to a first side of the first interposer; a second CoW device having a second interposer and a second die attached to a first side of the second interposer, the second interposer being laterally spaced apart from the first interposer; and a redistribution structure extending along a second side of the first interposer opposing the first side of the first interposer and extending along a second side of the second interposer opposing the first side of the second interposer, the redistribution structure extending continuously from the first CoW device to the second CoW device.

Semiconductor device and method of forming the same

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Integrated circuit package and method of forming same

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.

Manufacturing method of semiconductor package

A method includes forming a first photonic package, wherein forming the first photonic package includes patterning a silicon layer to form a first waveguide, wherein the silicon layer is on an oxide layer, and wherein the oxide layer is on a substrate; forming vias extending into the substrate; forming a first redistribution structure over the first waveguide and the vias, wherein the first redistribution structure is electrically connected to the vias; connecting a first semiconductor device to the first redistribution structure; removing a first portion of the substrate to form a first recess, wherein the first recess exposes the oxide layer; and filling the first recess with a first dielectric material to form a first dielectric region.

Photonic semiconductor device and method of manufacture

A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.

Optical transceiver and manufacturing method thereof

A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.

Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.

Semiconductor devices and methods of manufacture

In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

Semiconductor die package and method of manufacture

Growing community of inventors

Jubei, Taiwan

Shang-Yun Hou