Taiwan Semiconductor Manufacturing Comp. Ltd.

Shang-Yen Wu

Chiang-Ming Chuang

Hsin-Chi Chen

Hsun-Ying Huang

Chih-Ming Lee

Chao-Ching Chang

Tsung-Wei Huang

Yi-Chuan Lin

Chih-An Yang

Hung-Wei Ho

Chi-Cherng Jeng

Volume Chien

I-Chih Chen

Ying-Hao Chen

Fu-Tsun Tsai

Ping-Pang Hsieh

Yi-Sheng Liu

A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.

Semiconductor device structure and methods of forming the same

Provided is a method of manufacturing a semiconductor device including: providing a substrate having a memory cell region and a logic region; forming a plurality of stack structures on the substrate in the memory cell region; forming a polysilicon layer to cover the plurality of stack structures and the substrate in the logic region; performing a chemical-mechanical polishing (CMP) process on the polysilicon layer to expose top surfaces of the plurality of stack structures; and after performing the CMP process, patterning the polysilicon layer to form an erase gate between adjacent two stack structures and form a logic gate on the substrate in the logic region, wherein the logic gate has a topmost top surface lower than a topmost top surface of the erase gate.

Method of manufacturing semiconductor device

Provided is a semiconductor device including a substrate, a plurality of memory cells, and at least one dummy gate structure. The substrate has a memory cell region and a dummy region. The memory cells are disposed on the substrate in the memory cell region. Each memory cell includes: adjacent two stack structures disposed on the substrate; two select gates respectively disposed outside the adjacent two stack structures; and an erase gate disposed between the adjacent two stack structures. The erase gate has a step between a topmost top surface and a lowermost top surface of the erase gate. The at least one dummy gate structure is disposed on the substrate in the dummy region.

Semiconductor device

A method of manufacturing a semiconductor device includes following steps. The substrate has a dummy region and a memory cell region. A plurality of first stack structures are formed over the substrate in the memory cell region. At least one second stack structure is formed over the substrate in the dummy region. A conductive layer is formed over the substrate to cover the first stack structures and the at least one second stack structure. A planarization process is performed on the conductive layer to expose top surfaces of the first stack structures and the at least one second stack structure. The conductive layer is patterned to form an erase gate between adjacent two first stack structures, and to form first and second select gates outside the adjacent two first stack structures.

Manufacturing method of semiconductor device

A semiconductor device including a light sensing region disposed on a substrate is provided that includes a bond structure having one or more patterned layers underlying the pad element. The pad element may be coupled to the light sensing region and may be formed in a first metal layer disposed on the substrate. A second metal layer of the device has a first bond region, a region of the second metal layer that underlies the pad element. This first bond region of the second metal layer includes a pattern of a plurality of conductive lines interposed by dielectric. A via connects the pad element and the second metal layer.

Pad structure layout for semiconductor device

A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is formed in the semiconductor substrate, and includes an isolation oxide and a spin coating material. The isolation oxide is peripherally enclosed by the semiconductor substrate. The spin coating material is peripherally enclosed by the isolation oxide.

Method for forming a semiconductor device with void-free shallow trench isolation

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Tainan, Taiwan

Shang-Yen Wu