Taiwan Semiconductor Manufacturing Comp. Ltd.

Shang Y Hou

Shin-Puu Jeng

Hao-Yi Tsai

Chi-Hsi Wu

Chenming Hu

Pei-Haw Tsao

Hsin-Hui Lee

Chao-Yuan Su

Chender Huang

Harry Chuang

Yung-Shun Chen

Victor C Y Chang

A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area Ais defined on the first scribe line and is defined by the equation A=D&#xd7;S, where Dis the distance from the corner point of the die toward the main area of the die, and Sis the width of the first scribe line. Free area Ais defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation A=S&#xd7;S, where Sis the width of the second scribe line.

Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling

A method of forming a metal fuse comprising the following steps. A structure is provided having exposed adjacent metal structures. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having via openings 2 exposing at least a portion of the exposed adjacent metal structures. A metal fuse portion is formed between at least two of the adjacent metal structures without additional photolithography, etch or deposition processes. The metal fuse portion including a portion having a nominal mass and a sub-portion of the portion having a mass less than the nominal mass so that the metal fuse portion is more easily disconnected at the less massive sub-portion during programming of the metal fuse portion.

Metal fuse for semiconductor devices

A new method to determine a parameter of a damascene interconnect in an integrated circuit device is achieved. Drawn dimensions and local pattern density of a damascene interconnect are extracted in an integrated circuit device. A parameter of the damascene interconnect is calculating using the drawn dimensions and the local pattern density to select a per unit value from a set of per unit values measured over a range of drawn dimension and pattern density combinations. The method may be used to improve the accuracy of extracted damascene metal line resistance and parasitic capacitance.

Methodology to characterize metal sheet resistance of copper damascene process

A method of forming a metal fuse comprising the following steps. A structure is provided having exposed adjacent metal structures. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having via openings 2exposing at least a portion of the exposed adjacent metal structures. A metal fuse portion is formed between at least two of the adjacent metal structures without additional photolithography, etch or deposition processes. The metal fuse portion including a portion having a nominal mass and a sub-portion of the portion having a mass less than the nominal mass so that the metal fuse portion is more easily disconnected at the less massive sub-portion during programming of the metal fuse portion.

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Hsinchu, Taiwan

Shang Y Hou