United Microelectronics Corp.

Shang-Jr Chen

Ta-Kang Lo

Tsai-Fu Chen

Hung-Chang Chang

Chia-Chen Tsai

Der-Yuan Wu

Cheng-Guo Chen

Steve S Chung

Chun-Chia Chen

Kun-Yuan Wu

Chien-Kuo Yang

Po-Kang Yang

Chiu-Sheng Ho

Tai-You Chen

Shuo-Lin Hsu

Hsin-Ta Hsieh

Chen-Chien Li

First, a substrate having a first region and a second region is provided, a first gate structure is formed on the first region and a second gate structure is formed on the second region, an interlayer dielectric (ILD) layer is formed around the first gate structure and the second gate structure, and the first gate structure and the second gate structure are removed to expose the substrate on the first region and the second region. Next, part of the substrate on the first region is removed to form a first recess and part of the substrate on the second region is removed to form a second recess, in which the depths of the first recess and the second recess are different. Next, a first metal gate is formed on the first region and a second metal gate is formed on the second region.

Method for fabricating semiconductor device

A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.

Semiconductor device and method of manufacturing the same

A manufacturing method of a semiconductor device includes the following steps. A first gate dielectric layer is formed in a first gate trench and a second gate dielectric layer is formed in a second gate trench. A first bottom barrier layer is formed on the first gate dielectric layer and the second gate dielectric layer. A first conductivity type work function layer is formed on the first bottom barrier layer. A first treatment to the first gate dielectric layer and/or a second treatment to the first bottom barrier layer on the first gate dielectric layer are performed before the step of forming the first conductivity type work function layer. The first treatment and the second treatment are used to modify threshold voltages of specific transistors, and thicknesses of work function layers formed subsequently may be modified for increasing the related process window accordingly.

Manufacturing method of semiconductor device

A semiconductor device and method of manufacturing the same are provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.

A low leakage charge pumping (CP) method has been implemented for direct determination of interface traps in ultra-short gate length MOS devices with ultra-thin gate oxide in the direct tunneling regime. The leakage current in a 12 &angst;-16 &angst; gate oxide can be removed from the measured CP current, which enables accurate determination of the interface traps. This method has been demonstrated successfully for variousRTNO grown and RPN treated oxide CMOS devices with very thin gate oxide. It can be used as a good monitor of ultra-thin gate oxide process and the evaluations of device reliabilities in relation to the interface trap generation. In addition, the current method can be used to determine the physical channel length of CMOS devices.

Direct determination of interface traps in MOS devices

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Tainan, Taiwan

Shang-Jr Chen