Vanguard International Semiconductor Corporation

Shang-Hui Tu

Shin-Cheng Lin

Jui-Chun Chang

Chia-Hao Lee

Wen-Hsin Lin

Yu-Hao Ho

Rudy Octavius Sihombing

Tsung-Hsiung Lee

Chih-Jen Huang

Hung-Shern Tsai

Manoj Kumar

Priyono Tri Sulistyanto

Gene Sheu

Chih-Cherng Liao

Yeh-Ning Jou

Geeng-Lih Lin

Kwang-Ming Lin

Pei-Heng Hung

Yu-Lung Chin

Chen-Wei Wu

Yih-Jau Chang

Wen-Cheng Lin

Hsiung-Shih Chang

Karuna Nidhi

Rahul Kumar

Shao-Ming Yang

Neelam Agarwal

Yi-Fong Chang

Nithin Devarajulu Palavalli

Jimmy Lin

Ming-Horng Hsiao

A semiconductor device, including an insulator formed on a top surface of a semiconductor substrate, a semiconductor layer, containing a first region of a first conductivity type, formed on the insulator layer, wherein the first region is a P+ region or an N+ region, a second region of a second conductivity type in direct contact with the first region and forming a P-N junction with the first region, wherein the P-N junction comprises a first portion parallel to the top surface of the semiconductor substrate, and the second region is the semiconductor substrate and partially covered by the semiconductor layer, a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region.

Semiconductor device including zener diode and method of manufacturing thereof

A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

Method and apparatus for power device with multiple doped regions

A lateral double diffused metal-oxide-semiconductor device includes: an epitaxial semiconductor layer disposed over a semiconductor substrate; a gate dielectric layer disposed over the epitaxial semiconductor layer; a gate stack disposed over the gate dielectric layer; a first doped region disposed in the epitaxial semiconductor layer from a first side of the gate stack; a second doped region disposed in the epitaxial semiconductor layer from a second side of the gate stack; a third doped region disposed in the first doping region; a fourth doped region disposed in the second doped region; an insulating layer covering the third doped region, the gate dielectric layer, and the gate stack; a conductive contact disposed in the insulating layer, the third doped region, the first doped region and the epitaxial semiconductor layer; and a fifth doped region disposed in the epitaxial semiconductor layer under the conductive contact.

Lateral double diffused metal-oxide-semiconductor device and method for fabricating the same

A semiconductor device includes: a semiconductor substrate; a semiconductor layer disposed over the semiconductor layer; a first well region disposed in the semiconductor layer and the semiconductor substrate; a second well region disposed in the semiconductor layer; a first isolation element disposed in the first well region; a second isolation element disposed in the second well region; a gate structure disposed in the semiconductor layer between the first isolation element and the second isolation element; a first doped region disposed in the first well region; and a second doped region disposed in the second well region. The bottom surface of the gate structure is above, below or substantially level with a bottom surface of the first isolation structure.

Semiconductor device and method for fabricating the same

The invention provides a semiconductor device, including: a substrate of a first conductivity type having an active region and a termination region; an epitaxial layer of the first conductivity type over the substrate; a plurality of first trenches and second trenches in the epitaxial layer; an implant blocker layer formed at bottoms of the first and second trenches; a liner of a second conductivity type different from the first conductivity type conformally formed along sidewalls of the first and second trenches; a dielectric material filled in the first and second trenches defining a plurality of first columns and a plurality second column, respectively; a gate dielectric layer over the epitaxial layer; two floating gates formed on the gate dielectric layer; a source region; an inter-layer dielectric layer; and a contact plug formed on the source region.

A semiconductor device is provided. The semiconductor device includes a substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed on the substrate. The semiconductor device further includes a well region having a first doping concentration of a second conductivity type disposed in the epitaxial structure and the substrate. The semiconductor device further includes a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. The semiconductor device further includes a body region of the first conductivity type disposed under the source region, and a pair of first and second doped regions disposed in the well region between the drain region and the source region. The first and second doped regions extend outside of the well region and toward the body region.

Method and apparatus for power device with depletion structure

The invention provides a semiconductor device. A buried layer is formed in a substrate. A first deep trench contact structure is formed in the substrate. The first deep trench contact structure comprises a conductor and a liner layer formed on a sidewall of the conductor. A bottom surface of the first deep trench contact structure is in contact with the buried layer.

Semiconductor device and fabrication method thereof

A semiconductor device includes a semiconductor substrate and a semiconductor layer formed thereover. A gate structure is disposed over the semiconductor layer, and a first doped region is disposed in the semiconductor layer adjacent to a first side of the gate structure. A second doped region is disposed in the semiconductor layer adjacent to a second side of the gate structure opposite to the first side. A third doped region is disposed in the first doped region. A fourth doped region is disposed in the second doped region. A plurality of fifth doped regions is disposed in the second doped region. A sixth doped region is disposed in the semiconductor layer under the first doped region. A conductive contact is formed in the third doped region and the first doped region.

A semiconductor device includes: a semiconductor layer; a first doped well region disposed in a portion of the semiconductor layer; a first doped region disposed in the first doped well region; a second doped well region of an asymmetrical cross-sectional profile disposed in another portion of the semiconductor layer; second, third, and fourth doped regions formed in the second doped well region; a first gate structure disposed over a portion of the semiconductor layer, practically covering the second doped well region; and a second gate structure embedded in a portion of the semiconductor layer, penetrating a portion of the second doped well region.

A semiconductor device includes a semiconductor layer formed over a semiconductor substrate. A well region is disposed in a portion of the semiconductor layer, and a plurality of first doped regions is disposed in various portions of the well region. A second doped region is disposed in a portion of the well region. An isolation element is disposed in a portion of the top-most one of the first doped regions, and a third doped region is disposed in a portion of the top-most one of the first doped regions. A fourth doped region is disposed in a portion of the second doped region. An insulating layer overlies the third doped region, the isolation element, the second doped region, and the fourth doped region, and a conductive layer overlies the insulating layer.

Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A Pdoped drain region is disposed in the high-V N-well. A Pdiffused region and an Ndoped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the Ndoped source region and the other end extending over the insulation region.

Growing community of inventors

Jhubei, Taiwan

Shang-Hui Tu