Taiwan Semiconductor Manufacturing Comp. Ltd.

Shang-chih Hsieh

Lee-Chung Lu

Jerry Chang Jui Kao

Chi-Lin Liu

Chih-wei Chang

Greg Gruber

Ming-Chang Kuo

Meng-kai Hsu

You-cheng Lai

Pei-Wei Liao

Shi-han Zhang

A method including: providing a design data of an integrated circuit (IC), the design data comprising a first cell; identifying a first conductive line in the first cell as a critical internal net of the first cell, wherein the first conductive line is electrically connected between an input terminal of the first cell and an output terminal of the first cell; providing a library of the first cell, wherein the library includes a table of timing or power parameters of the first cell based on a multidimensional input set associated with the critical internal net; updating the design data by determining a timing or power value of the first cell based on the table; performing a timing analysis on the updated design data; and forming a photomask based on the updated design data.

Standard cell characterization for internal conductive line of cell

An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.

Flip-flop device and method of operating flip-flop device

Growing community of inventors

TAOYUAN COUNTY, Taiwan

Shang-chih Hsieh