Faraday Technology Corporation

Shang-Chih Hsieh

Jeng-Huang Wu

Hsin-Shih Wang

Chih-Chiang Hsu

Ming-Hsin Ku

Tzu-Pin Shen

Yi-Hwa Chang

Chang-Yu Wu

A power supply architecture for a structural application-specific integrated circuit (ASIC) is provided. The power supply architecture includes a first conductor and a second conductor. The first conductor is coupled to a fixed voltage. The first conductor at least passes through two edges of a cell. The first conductor and the second conductor are connected through a contact. The second conductor at most passes through one edge of the cell. The structural ASIC includes a first metal layer and a second metal layer. The first metal layer includes the first conductor. The second metal layer includes the second conductor.

Power supply architecture for structural ASIC

A timing measurement circuit inside a memory chip delays balanced test signals for generating delayed test signals. Each of the delayed test signals is input a corresponding input pin of a memory subsystem of the memory chip. By adjusting delay amount of the delayed test signals, AC timing parameters of the memory subsystem are tested and measured. When the timing measurement circuit is in ring oscillation, a resolution thereof is measured.

Method and apparatus for memory AC timing measurement

The present invention discloses a register circuit. The register circuit includes a latch circuit for latching an input data to generate an output data; an input signal selecting circuit, coupled to a non-test data and a test data respectively, for selectively outputting the non-test data or the test data as the input data; a control circuit, coupled to a driving clock, for controlling the latch circuit to latch the input data as the output data according to the driving clock; and a scanning circuit, coupled to the driving clock and the latch circuit, for scanning the output data of the latch circuit to generate a scanning data according to the driving clock.

Register circuit, scanning register circuit utilizing register circuits and scanning method thereof

A power gating circuit of a signal processing system includes a low dropout linear regulator, a control circuit, and an output circuit. The low dropout linear regulator includes a first transistor, an operational amplifier, a first resistor, a second resistor, and an output end. The output circuit includes a fourth transistor and a step-down circuit. The control circuit controls output voltage of the output circuit according to a control signal.

Growing community of inventors

Kaohsiung County, Taiwan

Shang-Chih Hsieh