Macronix International Co., Ltd.

Macronix Internationalco., Ltd.

Shang-Chi Yang

Chun-Hsiung Hung

Ken-Hui Chen

Kuen-Long Chang

Su-Chueh Lo

Jian-Syu Lin

Chun-Yu Liao

Hui-Yao Kao

Jhen-Sheng Chih

Fu-Nian Liang

Tung-Yu Li

Hang-Ting Lue

Teng-Hao Yeh

Chin-Hung Chang

Chang-Ting Chen

Chih-He Chiang

Kuan-Ming Lu

Yi-Huang Liu

Yen-Ning Chiang

Che-Wei Liang

Chung-Han Wu

Chun-Hao Tsai

Szu-yu Ko

Yi-Wei Chang

Electronic circuits, memory devices, and methods for compensating for data distortion from channel loss are provided. In one aspect, an electronic circuit includes a converter circuit configured to convert an input signal to a digital signal and a compensation circuit coupled to the converter circuit. The converter circuit includes a sampling circuit configured to receive the digital signal and generate an output signal. The output signal includes a stream of bits to be transmitted at a plurality of consecutive clock cycles. The converter circuit also includes one or more equalizing circuits coupled to the sampling circuit. Each equalizing circuit is configured to receive a bit of an output feedback signal at one of the consecutive clock cycles. The sampling circuit is configured to generate the output signal based on the digital signal and a sum of one or more equalization outputs of the one or more equalizing circuits.

Decision feedback equalization in semiconductor devices

Systems, devices, methods, and circuits for managing reference currents in semiconductor devices. In one aspect, a semiconductor device includes: a memory cell array configured to store data in sets of memory cells and circuitry coupled to the memory cell array. Each set of one or more sets of memory cells in the memory cell array is associated with a respective reference current, and memory cells in sets associated with different reference currents have different threshold voltage distributions. The circuitry is configured to: determine information associated with a reference current for a set of memory cells in the memory cell array based on a memory address corresponding to the set, generate the reference current based on the information associated with the reference current for the set, and sense one or more memory cells in the set based on the reference current.

Managing reference currents in semiconductor devices

A receiver circuit has a first stage circuit having a first stage input and a first stage output, the first stage output setting a first stage common mode voltage; a second stage circuit having a second stage input connected to the first stage output, and a second stage output setting a second stage common mode voltage; and a buffer circuit having a trip point voltage, connected to the second stage output. The first stage circuit can include circuit elements configured to establish the first stage common mode voltage so that the second stage common mode voltage matches the trip point voltage. The second stage circuit can include a self-biased amplifier.

High-speed, low distortion receiver circuit

A three dimension memory device, such as an AND-type memory, includes a memory cell tile, multiple source line switches, multiple first bit line switches to fourth bit line switches. The memory cell tile is divided into a first and a second memory cell sub-tiles. The first bit line switches are respectively coupled to multiple first bit lines of a first part of the first memory cell sub-tile. The second bit line switches are respectively coupled to multiple second bit lines of a second part of the first memory cell sub-tile. The third bit line switches are respectively coupled to multiple third bit lines of a first part of the second memory cell sub-tile. The fourth bit line switches are respectively coupled to multiple fourth bit lines of a second part of the second memory cell sub-tile.

Three dimension memory device capable of improving sensing accuracy in high-speed data sensing operation

A memory device, a failure bits detector, and a failure bits detection method thereof are provided. The failure bits detector includes a current generator, a current mirror, and a comparator. The current generator generates a first current according to a reference code. The current mirror mirrors the first current to generate a second current at a second end of the current mirror. The comparator compares a first voltage at a first input end with a second voltage at a second input end to generate a detection result.

Memory device, failure bits detector and failure bits detection method thereof

A continuous time linear equalizer (CTLE) circuit is provided. The CTLE circuit can include a differential pair of first and second transistors, the first and second transistors having drains connected through first and second drain resistors to a drain-side supply voltage node, and sources connected together by a source resistor and connected to one or more current sources, the first transistor in the differential pair having a gate connected to a reference voltage, and the second transistor in the differential pair having a gate connected to an input voltage, the drains of the first and second transistors providing a differential pair of signals as an output voltage, a first coupling capacitor connected between the source of the first transistor and the input voltage, and a second coupling capacitor connected to the source of the second transistor.

Continuous time linear equalizer of single-ended signal with input coupling capacitor

Systems, methods, circuits, and apparatuses for managing integrated circuits in memory devices are provided. In one aspect, an integrated circuit includes: a latch circuit including a latch and a sensing transistor coupled to the latch, and a compensation circuit coupled to the sensing transistor. The sensing transistor includes a gate terminal coupled to a sensing node and an additional terminal coupled to the compensation circuit, and the compensation circuit is configured to apply a control voltage to the additional terminal to compensate for a variation of a threshold voltage of the sensing transistor.

Threshold voltage variation compensation in integrated circuits

Systems, methods, circuits, and apparatus including computer-readable mediums for managing page buffer circuits in memory devices are provided. In one aspect, a memory device includes a memory cell array, memory cell lines connecting respective lines of memory cells, and a page buffer circuit including page buffers coupled to the memory cell lines. Each page buffer includes a sensing latch circuit and a storage latch circuit. The sensing latch circuit includes a sensing transistor coupled to a sensing node and at least one sensing latch unit having a first node coupled to the sensing node and a second node coupled to a first terminal of the sensing transistor. The storage latch circuit includes at least one storage latch unit having third and fourth nodes coupled to the sensing node and a gate terminal of the sensing transistor. A second terminal of the sensing transistor is coupled to a ground.

Managing page buffer circuits in memory devices

Systems, methods, circuits, devices, and apparatus including computer-readable mediums for managing reference voltages, e.g., with current compensation, in memory systems, e.g., non-volatile memory systems. In one aspect, an integrated circuit includes: an operational amplifier configured to receive input voltages and a supply voltage and output a control voltage based on the input voltages and the supply voltage; an output circuitry configured to receive the control voltage from the operational amplifier and the supply voltage, provide the input voltages to the operational amplifier, and output a reference voltage; and a compensation circuitry coupled to the output circuitry and configured to output a compensation current to compensate the output circuitry such that the reference voltage is substantially constant. The output circuitry is configured to generate the reference voltage based on the control voltage and the compensation current.

Managing reference voltages in memory systems

A sense amplifying device includes a bit line bias voltage adjuster and a sense amplifying circuit. The bit line bias voltage adjuster receives a power voltage to be an operation voltage. The bit line bias voltage adjuster includes a first amplifier, a first transistor and a first current source. The first amplifier, based on the power voltage, generates an adjusted reference bit line voltage according to a reference bit line voltage and a feedback voltage. The first transistor receives the adjusted reference bit line voltage and generates the feedback voltage, wherein the first transistor is a native transistor. The sense amplifying circuit receives the power voltage to be the operation voltage, and generates a sensing result according to the adjusted reference bit line voltage.

Memory and sense amplifying device thereof

An integrated circuit with a power-on-reset circuit includes an inverter circuit connected between the first and second supply node, a cascode-connected series of transistors MCn, for n going from 1 to N, connected between the first supply node and the input node of the inverter, and a resistive element connected between the input node of the inverter and the second supply node. The transistors in the cascode-connected series of transistors MCn pull up the input node voltage above a trip point voltage when the voltage between the input node and the first supply node is more than a threshold of the cascode-connected series. A circuit connected between the first and second supply nodes is responsive to a POR pulse output by the inverter.

Robust power-on-reset circuit with body effect technique

Systems, methods, circuits, and apparatus for managing flip flop circuits are provided. In one aspect, a flip flop circuit includes a first sub-circuit having a first inner node between a first input node and a first output node, a second sub-circuit having a second inner node between a second input node and a second output node, and a third sub-circuit coupled between the first and second inner nodes. The third sub-circuit is configured to be: in an open state to conductively disconnect the first and second inner nodes, and in a close state to conductively connect the first and second inner nodes, such that a first output at the first output node corresponds to a second input at the second input node and a second output at the second output node corresponds to a first input at the first input node.

Managing flip flop circuits

Systems, methods, circuits, and apparatus including computer-readable mediums for managing bit line voltage generating circuits in memory devices are provided. An example bit line voltage generating circuit is configured to provide a stable clamping voltage to at least one bit line connecting memory cells in the memory device. The bit line voltage generating circuit includes an operational amplifier configured to receive a reference voltage, a feedback voltage, and a compensation current and output an output voltage, and an output transistor configured to provide a terminal voltage as the feedback voltage and the output voltage as a target voltage that is associated with the clamping voltage. The operational amplifier is configured to be unbalanced such that the terminal voltage is smaller than the reference voltage, and the compensation current is configured to compensate the operational amplifier such that the clamping voltage is substantially constant and independent from PVT (Process-Voltage-Temperature) effect.

Managing bit line voltage generating circuits in memory devices

A circuit to generate complementary signals comprises a first string of inverters with two inverters in series to produce a true signal in response to an input signal, and a second string of inverters with three inverters in series to produce a complement signal in response to the input signal. A compensation capacitance circuit is connected to a node in the first string of inverters. The compensation capacitance circuit can add capacitance to the node to increase a resistance-capacitance RC delay at the node in a manner which emulates the delay across PVT conditions an inverter in the second string of inverters.

Low-skew complementary signal generator

An in-memory multiply and accumulate circuit includes a memory array, such as a NOR flash array, storing weight values W. A row decoder is coupled to the set of word lines, and configured to apply word line voltages to select word lines in the set. Bit line bias circuits produce bit line bias voltages for the respective bit lines as a function of input values Xon the corresponding inputs. Current sensing circuits are connected to receive currents in parallel from a corresponding multimember subset of bit lines in the set of bit lines, and to produce an output in response to a sum of currents.

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Changhua, Taiwan

Shang-Chi Yang