Hewlett-packard Development Company, L.P.

Compaq Information Technologies Group, L.p.

Intel Corporation

Mellanox Technologies, Ltd.

Tilera Corporation

Shane Bell

Daniel William Bailey

Matthew C Mattina

Jeffrey D Pickholtz

Mark B Rosenbluth

Anant Agarwal

Carl Ramey

Matthew Mattina

David M Wentzlaff

Ian Rudolf Bratt

Bruce Edwards

Christopher J Jackson

Richard Schooler

Christopher D Metcalf

Liewei Bao

Chyi-Chang Miao

Patrick Robert Griffin

William Johnson Bowhill

Richard B Watson, Jr

Kenneth M Steele

Matthew H Reilly

John A Amann

Mathew Hostetter

Andrew Carlson

Richard Conlin

Chuan-Hua Chang

Ben Harrison

Kevin Joyce

Christine Deignan

A computing system comprises one or more core processors coupled to a communication network among the cores via a switch in each core and switching circuitry to forward data among cores and switches. Features include a programmable classification processor for directing packets, techniques for managing virtual functions on an IO accelerator card, packet scheduling techniques, multi-processor communication using shared FIFOs, programmable duty cycle adjustment and delay adjustment circuits, a new class of instructions that use a ready bit, and cache coherence and memory ordering techniques.

Computing in parallel processing environments

A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

A mechanism detects multiple assertions in a bus efficiently by encoding each of N bus lines with log(N) pairs of bit lines.

Efficient detection of multiple assertions in a bus

A multi-threaded processor is configured to detect excepted instructions from a first program, and to stop fetching younger instructions from that same program, to thereby conserve system resources that can be used by other programs. Each fetched program instruction has an associated status bit, which is set if the instruction excepts. Each excepting instruction is logged in an exception logging unit, which causes the associated status bit to be set. Each program has an associated in-flight vector table that tracks the instructions that have been fetched for that program. The status bits are compared with the in-flight vector table to identify the program that is associated with an excepted instruction. That program is then disabled, thereby preventing further fetching of instructions for that program until the excepted instruction clears.

System and method to avoid resource contention in the presence of exceptions

An exception handler for a processor is split into two functional units to permit exceptions to be classified into two categories. The first category of exceptions includes performance critical excepted instructions, while the second category includes non-performance critical excepted instructions. The performance critical exceptions are routed to a speculative exception handler, which resolves the exceptions speculatively, even though the excepted instruction may lie in a speculative path of the program flow. The non-performance critical exceptions are routed to a non-speculative exception handler that only resolves exceptions when the excepted instruction is certain to execute in an actual path of the program flow.

Method and system with multiple exception handlers in a processor

A clock distribution system for a semiconductor device provides for both on-chip and in-package clock distribution via on-chip and in-package clock distribution networks. Each of these networks is selectively enabled depending on the mode of operation. Specifically, for wafer testing, the on-chip clock distribution network is selected. Thus, a probe tester need only provide a single clock source with conventional timing specifications to test the operation of the chip. In contrast, during normal operation, an in-package clock distribution network is enabled. In-package clock routing provides the lowest variation mode and thus, will result in the maximum clock frequency for the chip.

Dual on-chip and in-package clock distribution system

A method and apparatus are provided for ensuring that a clocked circuit will function after fabrication, regardless of the presence of clock skew. More particularly, a method and apparatus are shown for de-skewing the clock signals of such a clocked circuit only when clock skew is present. When such clock skew does not develop, peak performance of the associated circuit can be achieved by turning off the de-skewing function without removing that functionality from the circuit.

Method and apparatus to enforce clocked circuit functionality at reduced frequency without limiting peak performance

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Shane Bell