Tektronix, Inc.

Shane A Hazzard

Patrick A Smith

Que Thuy Tran

David L Kelly

Daniel S Froelich

Daniel G Knierim

Jed H Andrews

Sarah R Boen

Sam J Strickling

John C Calvin

Michelle L Baldwin

Lin-Yung Chen

Jonathan San

Kayla R Klingman

A calibrated test and measurement cable for connecting one or more devices under test and a test and measurement instrument, including a first port structured to electrically connect to a first signal lane, a second port structured to electrically connect to a second signal lane, a third port structured to electrically connect to a test and measurement instrument, and a multiplexer configured to switch between electrically connecting the first port to the third port and connected the second port to the third port. The first and second signal lanes can be included on the same device under test or different devices under test. An input can receive instructions to operate the multiplexer.

Multiplexer-enabled cables and test fixtures

Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link of a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

Systems, methods and devices for high-speed input/output margin testing

A test and measurement apparatus, system, and method for synchronizing an acquisition or triggering system to a specific burst of interest. The subject apparatus and method triggers on varying energy content of a signal qualified by time in the presence of high-frequency input signal bursts, by using an adjustable pulse width envelope detector, disposed in the signal path of the trigger circuitry, as a digital rectifier or to otherwise process and extract an envelope signal. An RF envelope probe having an analog envelope detector among other suitable components is disclosed. A method is implemented for isolating an interval of interest in a signal under test. An envelope detector circuit produces an envelope signal from the signal. Trigger circuitry receives the envelope signal from the envelope detector, and isolates the interval of interesting in the signal under test using the envelope signal.

Apparatus and method for performing burst triggering in a test and measurement instrument

A dF/dT trigger system and method includes instantaneously triggering on a frequency deviation of a data signal, which can be associated with an SSC signal. After receiving a signal at an input terminal of a test and measurement instrument, the signal is low-pass filtered and transmitted to trigger circuitry. When a frequency deviation rate in the filtered signal exceeds or crosses one or more thresholds, a trigger event is produced. Also disclosed is a test and measurement instrument including an input terminal to receive the signal, input circuitry to receive and process the signal, and dF/dT trigger circuitry configured to receive the signal and produce a trigger event when a frequency deviation in the signal exceeds or crosses one or more thresholds.

DF/dT trigger system and method

A method for improving performance and flexibility of serial data analysis in test instruments, is independent of data bit rate, encoding scheme or communication protocol embodied in the serial data. The serial data is input to a transmitter section, where it is demultiplexed into a plurality of multi-bit lanes, such as n bits for each of N lanes. The N lanes are then encoded into characters, the encoded N lanes having m bits per lane where m&#x3e;n. Bit stuffing is used to adjust the data rate and/or to insert qualifiers. The stuffed, encoded N lanes are then multiplexed into N serial lanes, which are output from the transmitter section for input to a receiver section at a data rate that is optimal for the receiver section. In the receiver section the N lanes are deserialized, decoded and input to a word recognizer to generate a trigger event signal.

Serial data analysis improvement

Growing community of inventors

Cornelius, OR, United States of America

Shane A Hazzard