Globalfoundries Singapore Pte. Ltd.

Shan Ryan

Manjunatha Govinda Prabhu

Mahadeva Iyer Natarajan

Da-Wei Lai

A clamp circuit includes both nmos and pmos devices connected in series between a voltage source terminal, such as an integrated circuit pad, and ground. A trigger unit, connected between the voltage source and ground, includes a plurality of output terminals coupled to the clamp circuit. The trigger unit is responsive to a voltage threshold, such as caused by an ESD occurrence, between the voltage source and ground to apply clamping signals at its output terminals to couple the voltage source terminal to ground through both nmos and pmos devices.

Power clamp for high voltage integrated circuits

A driver-based distributed multi-path ESD scheme is disclosed. Embodiments include providing a plurality of I/O cells, wherein each of the I/O cells includes a first driver having a first source, a first drain, and a first gate; and providing a first signal to turn on the first driver in each of the I/O cells during an ESD event to form a plurality of parallel ESD paths that include turned-on first drivers.

Growing community of inventors

Singapore, Singapore

Shan Ryan