Anokiwave, Inc.

Shamsun Nahar

Scott R Humphreys

Kartik Sridharan

Gaurav Menon

Jun Li

Akhil Garlapati

Antonio Geremia

Vipul Jain

Nitin Jain

Robert J McMorrow

Kristian N Madsen

Noyan Kinayman

Eythan Familier

David W Corman

Kevin B Greene

Susanne A Paul

Jason Leo Durbin

Amir Esmaili

Pavel Brechko

Chad Cookinham

Mikhail Shirokov

A time-to-digital converter (TDC) uses voltage as a representation of time offset. A voltage change is induced over a time period from a start signal to a stop signal. The final voltage is then measured, and the voltage measurement is mapped to a time value representing the time between the start signal and the stop signal. The voltage change can be increasing or decreasing, e.g., by charging or discharging a capacitive circuit between the start signal and the stop signal. The voltage can be measured using an analog-to-digital converter (ADC) or other voltage measurement circuit. The voltage measurement can be mapped to the time value in any manner, such as, for example, using a transfer function or using a mapping table that provides a time value for each possible voltage measurement value.

Time-to-digital converter using voltage as a representation of time offset

A method and/or apparatus for tuning a frequency synthesizer device toward a prescribed frequency may input a signal into the input of the frequency synthesizer to produce an output signal having an output frequency, select a first one of a set of the above noted prescribed coarse curves, and compare the magnitude of the difference between the prescribed frequency and the output frequency. Next, the method selects a second of the set of coarse curves as a function of the magnitude of the difference between the prescribed frequency and the output frequency. Preferably, the method selects the second of the set of coarse curves by selecting one or more of the coarse curves out of the sequential frequency order as a function of the magnitude of the difference between the prescribed frequency and the output frequency.

Method and apparatus for tuning a synthesizer

Digital post-processing of time-to-digital converter (TDC) output data can be used to map each TDC code to the ideal one, but this requires knowing the TDC input-output mapping. Therefore, a calibration system and method are provided for characterizing operation of a TDC to compensate for non-idealities. Input signals having a known time difference are provided to the TDC, and a mapping between the TDC output and the known time difference is stored in a mapping table. With the described method, it is possible to input an input ramp of very low slope to construct this mapping to a desired resolution during a background calibration procedure. This characterizing and mapping can be performed across a range of input signals having different known time differences. After calibration, a mapping table can be used by a mapping circuit of the TDC or by a digital post-processing function to provide a compensated TDC output.

Time-to-digital converter and calibration

Embodiments of the present invention synchronize multiple synthesizers, such as phase-locked loops (PLLs), in a manner that does not require communication or coordination between the synthesizers. Specifically, each synthesizer is part of a synthesizer circuit that includes a synthesizer (e.g., a PLL), a phase measurement circuit, and a synchronization circuit. A common reference signal (e.g., an alternating clock signal) is provided to the synthesizer circuits. In one exemplary embodiment, in each synthesizer circuit, the phase measurement circuit measures a phase difference between the reference signal and a corresponding output of the synthesizer, and the synchronization circuit adjusts the synthesizer operation based on the measured phase difference in such a way that all of the synthesizers operate in-phase with one another relative to the common reference signal, without having any communication or coordination between the two synthesizer circuits other than provision of the common reference signal.

Phase-aligning multiple synthesizers

A beamforming integrated circuit system is configured to optimize performance. Among other things, the system may run at a lower power than conventional integrated circuits, selectively disable branches to control certain system functions, and/or selectively position ground pads around receiving pads to enhance isolation. The system also may use a beamforming integrated circuit as a distribution circuit for a number of similar or like beamforming integrated circuits.

Beamforming integrated circuit, AESA system and method

A system and a method for calibrating an antenna using trim bits and non-volatile memory is disclosed. In one aspect, an apparatus includes a power amplifier configured to at least amplify the output signal of the first antenna. The power amplifier includes multiple stages. The apparatus further includes a trim control circuit configured to adjust a bias of one of the stages of the power amplifier, using trim bits from non-volatile memory. The trim control circuit is further configured to scale the bias of one of the plurality of stages of the power amplifier by an integer between 0 and 2&#x2212;1 corresponding to a binary number formed by the first plurality of trim bits, wherein n corresponds to the number of trim bits.

Calibration of active electronically steered antennas using trim bits and non-volatile memory

Illustrative embodiments significantly improve RF isolation in a packaged integrated circuit by separating the pins/pads associated with multiple RF channels from one another and also from pins/pads associated with digital circuits. Specifically, in certain exemplary embodiments, the integrated circuit is configured with the pins/pad for the digital circuits on a first edge of the chip, the pins/pads for common RF signals on a second edge of the chip opposite the first edge, and the pins/pads for the individual RF channels on third and fourth edges of the chip. The pins/pads associated with each RF channel may include multiple pins/pads (an 'RF group') and may have a central RF pin/pad with a ground pin/pad on each side of the central RF pin/pad. One or more ground pins/pads may be placed between adjacent RF groups on a given edge of the chip.

Apparatus and method for RF isolation in a packaged integrated circuit

A beamforming integrated circuit system for use in a phased array has a microchip with RF circuitry, and a plurality of (on chip) interfaces electrically connected with the RF circuitry. The plurality of interfaces includes a signal interface, a first ground interface, and a second ground interface. The signal interface is configured to communicate an RF signal, and both the first and second ground interfaces are adjacent to the signal interface. The system also has a material ring circumscribing the plurality of interfaces, and at least one RF ground path coupled with the material ring.

Beamforming integrated circuit with RF grounded material ring

A beamforming integrated circuit system for use in a phased array has a microchip with RF circuitry, a bottom surface, and a plurality of interfaces electrically connected with the RF circuitry. The plurality of interfaces includes a plurality of static interfaces and a plurality of RF interfaces. The plurality of static interfaces are on the bottom surface of the microchip and adjacent to each other. The plurality of RF interfaces are also on the bottom surface of the microchip, but radially outward of the plurality of static interfaces. The microchip is configured to be flip chip mounted.

Growing community of inventors

San Diego, CA, United States of America

Shamsun Nahar