Texas Instruments Corporation

Shakti Shankar Rath

Vineet Mishra

Baher S Haroun

Visvesvaraya Appala Pentakota

Nitin Kumar Agarwal

Sami Issa

Anand Hariraj Udupa

Gautam Salil Nandi

Ravishankar S Ayyagari

Supriyo Palit

Abhaya Kumar

Rishubh Khurana

Suhas R Kulhalli

Sandeep Perdoor

Sindhuja Sridharan

Praveen Adil

Circuits and methods for reducing input dependent capacitor DAC switching current in flash-successive approximation register (SAR) analog-to-digital converters (ADCs) are disclosed. An ADC includes an M-bit flash ADC and N-bit SAR ADC. In flash conversion phase, flash ADC outputs digital signal including most significant M-bits of N-bits of digital output code for a sampled analog signal. SAR ADC includes capacitor DAC and digital engine. The capacitor DAC includes first and second set of capacitors, where first ends of the first and second set of capacitors are coupled to common terminal. The digital engine provides the N-bits of digital output code in SAR conversion phase based on the digital signal and a voltage (Vcom) at the common terminal. During flash conversion phase, second ends of the first set of capacitors are connected to Vref and Vgnd respectively so as to generate a voltage level corresponding to the digital signal as Vcom.

Reduction of input dependent capacitor DAC switching current in flash-SAR analog-to-digital converters

An input buffer for an Ultradeep Sub Micron (UDSM) process which allows the UDSM process to interface with a 3V input. The input voltage is applied to a degenerated transistor which forms part of the input buffer. The input buffer effectively drops the input voltage to a voltage suitable for use by the core of the UDSM process.

Input buffer in ultradeep submicron process

A residue block in a stage of a pipeline ADC processing differential signals contains multiple pairs of capacitors. During a hold phase of operation, one capacitor of a pair is connected to a positive reference voltage, and the other capacitor is connected to a negative reference voltage if the input signal exceeds a corresponding threshold voltage. When the input signal does not exceed the corresponding threshold voltage, both capacitors of the pair are connected either to the positive or the negative reference voltage. As a result, the need for a common mode reference voltage may be eliminated, and the residue block can be implemented with a smaller area.

DAC architecture for an ADC pipeline

A clamping circuit containing a transistor and a current amplifier. The transistor is designed to turn on when the voltage at a node exceeds (falls below) a specified upper (lower) level. The current amplifier is designed to draw substantial amount of current when the transistor is turned on to clamp the voltage at the node to the desired level.

Clamping circuit

A single integrated circuit (). The integrated circuit comprises a first circuit () having a data path, the first circuit consisting of a first number of logic gates for performing a plurality of logic functions. The integrated circuit also comprises a circuit () for indicating a potential speed capability of the data path. The circuit for indicating comprises a second number of logic gates () for performing the plurality of logic functions, wherein the second number is less than the first number. The circuit for indicating also comprises additional circuitry () for representing parasitic characteristics in the data path.

Integrated circuit dynamic parameter management in response to dynamic energy evaluation

A computer programmed to specify a design of a circuit for indicating a potential speed capability of a data path in a predetermined circuit. The data path comprises a plurality of logic functions to be performed by a first number of logic gates. The computer specifies the design by steps. In one step, the program specifies a second number of logic gates to be included in the circuit for indicating a potential speed capability. The second number of logic gates is less than the first number of logic gates and provides voltage and delay characteristics comparable to the data path. The computer also specifies additional circuitry to be included in the circuit for indicating a potential speed capability, wherein the additional circuitry is for representing parasitic characteristics in the data path.

Computer program for programming an integrated circuit speed capability indicator

Low voltage transistors are used in high voltage environment. The low voltage transistors may be used in the path of processing of a signal to increase the throughput performance. By using high voltage supply associated with the high voltage environment, a higher SNR may be attained. Various techniques are implemented to ensure that the low voltage transistors are not damaged by prolonged exposure to high voltages.

Enhancing SNR and throughput performance of integrated circuits

A low-jitter clock distribution circuit, used in an integrated circuit having multiple analog-to-digital converters (ADCs), includes a plurality of cascaded inverters, each inverter including an upper P-channel transistor connected to a lower N-channel transistor. The ratio Wp/Wn of the widths of the P-channel and N-channel transistors in each inverter is equal to substantially the square root of the ratio Un/Up of the majority carrier mobilities of the N-channel and P-channel transistors as determined by the semiconductor fabrication process.

Low-jitter clock distribution circuit

An offset is used to correct the output of a charge coupled device (CCD). The correction to the offset is determined by an exponential curve which allows for greater correction when error is large, and little correction when the error is small. The exponential curve may be viewed as a sequence of connected linear segments, and the correction to the offset may be determined by the slope of the segment to which the error maps. As the slopes at large errors are steep, the slope is correspondingly high, and the offset converges towards the correct value quickly. Power consumption is optimized by implementing the offset generation circuit using capacitor charge sharing principles.

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Bengaluru, India

Shakti Shankar Rath