University of Michigan

Qualcomm Incorporated

Shaizeen Aga

Satish Narayanasamy

Han Zhao

Gheorghe Calin Cascaval

Arun Raman

Dario Suarez Gracia

Pablo Montesinos Ortego

Behnam Robatmili

Aravind Natarajan

Abhayendra Singh

A system that executes private enclave functions in a secure high-performance host processor connected to an enhanced memory unit through a conventional memory bus using a packetized interface is disclosed. The logic layer of the enhanced memory unit is included in a trusted computing base (TCB) and is used to implement cryptographic functions. Storage layers of the enhanced memory unit remain outside the TCB and are used to store encrypted data and associated meta-data.

Trusted computing system with enhanced memory

Embodiments include computing devices, systems, and methods for task-based handling of repetitive processes in parallel. At least one processor of the computing device, or a specialized hardware controller, may be configured to partition iterations of a repetitive process and assign the partitions to initialized tasks to be executed in parallel by a plurality of processor cores. Upon completing a task, remaining divisible partitions of the repetitive process of ongoing tasks may be subpartitioned and assigned to the ongoing task, and the completed task or a newly initialized task. Information about the iteration space for a repetitive process may be stored in a descriptor table, and status information for all partitions of a repetitive process stored in a status table. Each processor core may have an associated local table that tracks iteration execution of each task, and is synchronized with the status table.

Method for exploiting parallelism in task-based systems using an iteration space splitter

A data processing system including multiple processorseach with a local cache memoryshare a main memoryunder control of a coherency controller. Store requests from a store requester which are to be serviced by data received from the main memorytrigger the coherency controllerto return exclusive rights to access the data to the store requester before the corresponding data is returned from the main memory. The store requester uses possession of the exclusive rights to access the data to permit further processing with an ordering constraint relative to the store request to proceed even though the store request has yet to be finished. The ordering constraint may be, for example, a fence instruction. The store requester in possession of the exclusive rights to access the data values ensures that the store request is finished and its results observed by any instruction as required by the ordering constraint it has released early.

Ordering constraint management within coherent memory systems

Growing community of inventors

Ann Arbor, MI, United States of America

Shaizeen Aga