Imec Vzw

Shairfe Muhammad Salahuddin

Alessio Spessot

Julien Ryckaert

Jan F Van Houdt

Hyungrock Oh

Bharani Chakravarthy Chava

A multiport memory cell for register files is disclosed. Vertically stacked top and bottom tier of the memory cell are electrically interconnected through a pair of vias and comprise each an active device layer and a metal layer stack. The memory cell is partitioned to have a latching circuit and at least one write port located in the bottom tier and at least two read ports in the top tier. A word line trace for controlling the at least one write port is formed in the bottom tier metal layer stack and comprises two terminal sections and one intermediate section oriented perpendicularly to the terminal sections. The intermediate section is arranged between the pair of vias in a height direction of the memory cell.

Multiport memory cells including stacked active layers

A synapse circuit with an arrayed structured memory for machine learning applications is disclosed. The synapse circuit comprises a controlled variable resistance, a controlled switch connected to a contact terminal of the controlled variable resistance, and a memory cell for storing a weight variable. The memory cell is operatively connected to a control terminal of the controlled switch. A control terminal of the controlled variable resistance is configured for receiving an activation signal. The controlled variable resistance has a first resistance value and a second resistance value substantially larger than the first resistance value. A ratio of the second resistance value to the first resistance value is at least one hundred. A current, flowing through the controlled switch and the controlled variable resistance, (1) is indicative of the activation signal weighted by the stored weight variable if the controlled variable resistance is the first resistance value and (2) is smaller or equal to one picoampere at room temperature if the controlled variable resistance is adopting the second resistance value.

Synapse circuit with memory

The disclosed technology generally relates to a memory selector and to a memory device including the memory selector, and more particularly to the memory selector and the memory device implemented in a crossbar memory architecture. In one aspect, a memory selector for a crossbar memory architecture comprises a metal bottom electrode, a metal top electrode and an intermediate layer stack between and in contact with the metal top and bottom electrodes. A bottom Schottky barrier having a bottom Schottky barrier height (&#x3a6;) is formed at the interface between the metal bottom electrode and the intermediate layer stack. A top Schottky barrier having a top Schottky barrier height (&#x3a6;) is formed at the interface between the metal top electrode and the intermediate layer stack. The disclosed technology further relates to a random access memory (RAM) and a memory cell including the memory selector.

Memory selector and memory device including same

A method for forming airgaps within an integrated electronic circuit implements a conformal layer and a nanosheet both of boron nitride. The method has advantages for the circuit due to special properties of boron nitride material. In particular, mechanical strength and heat dissipation are increased whereas electro-migration is limited. The method may be applied to the first interconnect layer of the integrated circuit, for reducing additionally capacitive interactions existing between gate electrode structures and source or drain contact structures.

Integrated electronic circuit with airgaps

The disclosed technology generally relates to semiconductor devices and methods of manufacturing semiconductor devices such as both logic and memory semiconductor devices. In one aspect, a semiconductor device includes a semiconductor substrate having a channel region between a source and a drain region, a gate structure arranged to control the channel region and a dielectric structure arranged between the channel region and the gate structure. The dielectric structure includes a high-k dielectric layer or a high-k ferroelectric layer and at least one two dimensional (2D) hexagonal boron-nitride (h-BN) layer in direct contact with the high-k dielectric layer or the high-k ferroelectric layer.

Semiconductor devices and methods of manufacturing semiconductor devices

The disclosed technology is generally directed to semiconductor integrated circuit devices and more particularly to a three-transistor random access memory (3T RAM) device, and a method of fabricating and operating the same. In one aspect, a 3T RAM cell includes a ferroelectric-based field effect transistor (FeFET) having a first gate connected as a storage node and a second transistor connected between the FeFET and a read bit line having a second gate connected to a read word line. The 3T RAM cell also includes a third transistor connected between the storage node and a write bit line having a third gate connected to a write word line.

Growing community of inventors

Leuven, Belgium

Shairfe Muhammad Salahuddin