Intel Corporation

Shailesh Shah

Altug Koker

Murali Ramadoss

Abhishek R Appu

Joydeep Ray

Elmoustapha Ould-Ahmed-Vall

Prasoonkumar Surti

Subramaniam M Maiyuran

Vasanth Ranganathan

Varghese George

Kamal Sinha

Ben J Ashbaugh

Nicolas C Galoppo Von Borries

Scott R Janus

Aravindh V Anantaraman

Lakshminarayanan Striramassarma

Mike MacPherson

Pattabhiraman K

Valentin Andrei

Brent E Insko

Vikranth Vemulapalli

Jonathan D Pearce

Arthur Hunter, Jr

Yoav Harel

Marian Alin Petre

Aditya Navale

Satish K Damaraju

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

Systems and methods for improving cache efficiency and utilization

Embodiments of an invention for dynamic error correction using parity and redundant rows are disclosed. In one embodiment, an apparatus includes a storage structure, parity logic, an error storage space, and an error event generator. The storage structure is to store a plurality of data values. The parity logic is to detect a parity error in a data value stored in the storage structure. The error storage space is to store an indication of a detection of the parity error. The error event generator is to generate an event in response to the indication of the parity error being stored in the error storage space.

Dynamic error handling using parity and redundant rows

Growing community of inventors

Folsom, CA, United States of America

Shailesh Shah