Lsi Logic Corporation

Shailesh I Shah

Satish Padmanabhan

Robert K Yu

Chakra R Srivatsa

A multiplication accumulation circuit (abbreviated as &ldquo;MAC&rdquo;) has five input buses that carry signals for operands A, B, C, D and E, a control bus that carries signals for controlling the operations performed on the received operands, and an output bus that carries a signal generated by the MAC. Each of operands A, B, C and D can be four different operands that are used as follows by the MAC: (1) to perform two multiplications simultaneously, and (2) to perform an addition of the products of the two multiplications and the fifth operand E, e.g. generate on the output bus a signal of value A*C&plus;B*D&plus;E. Alternatively, operands A and B can be, respectively, the upper and lower halves of a first double word to be used as a multiplicand. Similarly, operands C and D can be the upper and lower halves of a second double word to be used as a multiplier. In this case, the four operands A, B, C and D are used as follows by the MAC: (1) to perform a single multiplication of the first double word with the second double word, and (2) to perform an addition of the product of the double word multiplication, and the fifth operand E, e.g. generate on the output bus a signal of value &lsqb;A,B&rsqb;*&lsqb;C,D&rsqb;&plus;E.

Circuit and method for multiplying and accumulating the sum of two products in a single cycle

An instruction (also called a 'bit reversal instruction') for reversing the order of bits in an input signal is implemented by reusing one or more components in a datapath normally found in a processor. Specifically, a bit reversal instruction is implemented by reuse of a shifter unit normally used in a datapath to shift bits of an input signal. The shifter unit includes three stages: a first stage formed by a number of input multiplexers, a second stage formed by, for example, a left shifter, and a third stage formed by a number of output multiplexers. When using a left shifter to implement the bit reversal instruction, the input multiplexers are not used. Instead, the left shifter is used to shift bits of the input signal left by a number that is inverse of the number of bits to be reversed. Thereafter, the output multiplexers reverse the order of bits generated by the left shifter, thereby completing the bit reversal instruction. The shifter unit also implements a shift left instruction and a shift right instruction in the normal manner. Instead of using a left shifter, a right shifter can be used to implement the bit reversal instruction, wherein input multiplexers are used to reverse the order of bits, and output multiplexers are not used.

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Sunnyvale, CA, United States of America

Shailesh I Shah