Impinj, Inc.

Virage Logic Corporation

Shailendra Srinivas

Christopher J Diorio

Ronald A Oliver

Harley K Heinrich

Theron Stanford

Jay A Kuhn

John D Hyde

Ronald Lee Koepp

Alberto Pesavento

Chad A Lindhorst

Troy N Gilliland

An RFID IC may operate at a relatively low clock frequency while impedance matching to an antenna is being tuned to increase the amount of power that the IC can extract from an incident RF wave. A tuning circuit tunes the impedance matching by adjusting a variable impedance coupling the IC and the antenna. The IC may power-up with a low clock frequency or reduce its current clock frequency to a lower clock frequency prior to tuning or during the tuning process, and may increase its clock frequency upon completion of tuning or during the tuning process.

RFID tag clock frequency reduction during tuning

Embodiments are directed to a Radio Frequency Identification (RFID) integrated circuit (IC) having a first circuit block electrically coupled to first and second antenna contacts. The first antenna contact is disposed on a first surface of the IC and the second antenna contact is disposed on a second surface of the IC different from the first surface. The first and second antenna contacts are electrically disconnected from each other.

RFID integrated circuits with antenna contacts on multiple surfaces

A tuning circuit in an RFID tag may be used to match antenna and integrated circuit (IC) impedances to maximize the efficiency of IC power extraction from an incident RF wave. The tuning circuit, which requires less power to operate than the IC, adjusts a variable impedance to improve the impedance matching between the IC and the tag antenna and thereby increase the IC power extraction efficiency. The IC may begin operating according to a protocol when it extracts sufficient power from the RF wave or when an optimal impedance matching and power transfer is achieved.

Self tuning RFID tags

The present disclosure provides examples of a voltage regulator for a Radio Frequency Identification tag circuit. The voltage regulator includes a pair of native transistors. A first native transistor is coupled to a reference voltage and biased to saturation. A resistive element coupled between the gate and the drain of the transistor ensures a sufficient voltage difference between the source and the drain of the first native transistor. The second native transistor, with a gate coupled to the gate of the first native transistor, outputs a regulated voltage.

Voltage regulators using a resistive chain to bias a native transistor

Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge, and a capacitor structure for extracting charge from the gate, such as by tunneling. A counteracting circuit prevents extracting charge from the floating gate beyond a threshold, therefore preventing overtunneling or correcting for it. In one embodiment, the counteracting circuit supplies electrons to the floating gate, to compensate for tunneling beyond a point. In another embodiment, the counteracting circuit includes a switch, and a sensor to trigger the switch when the appropriate threshold is reached. The switch may be arranged in any number of suitable ways, such as to prevent a high voltage from being applied to the capacitor structure, or to prevent a power supply from being applied to a terminal of the transistor or to a well of the transistor.

Growing community of inventors

Seattle, WA, United States of America

Shailendra Srinivas