Nvidia Corporation

Ikanos Communications, Inc.

Shailendra Singh

James Leroy Deming

Wishwesh Anil Gandhi

Gregory Scott Palmer

Alan Menezes

Manas Mandal

Praveen Joginipally

Pranav Vaidya

Feiqi Su

Jerome Francis Duluk, Jr

Lacky V Shah

Samuel Hammond Duncan

Timothy John Purcell

Jonathon Stuart Ramsey Evans

Eric Rock

Sigurd Schelstraete

Amitkumar Mahadevan

Laurent Alloin

Nicholas Philip Sands

Sonata Gale Wen

Kevin Dean Fisher

Jonathon Stuart Ramsay Evans

A parallel processing unit (PPU), operating in a traditional processing environment or in a virtualized processing environment, can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

Techniques for configuring a processor to function as multiple, separate processors in a virtualized environment

A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

Techniques for configuring a processor to function as multiple, separate processors

Techniques for reconfiguring partitions in a parallel processing system

Methods, systems, and devices are described for wired communication. In one aspect, a method includes selecting a gain scalar based at least in part on a constellation point distance associated with a constellation mapper for a line and a tone. The method also includes applying the gain scalar to a tone data output signal of a vector processor.

Reduced precision vector processing

Residual FEXT resulting from intended and/or inherent partial cancellation of crosstalk in vectored DSL systems impairs upstream power back-off (UPBO) as traditionally implemented. By considering and taking into account the effects of residual crosstalk on vectored DSL system performance and operation, improved data rates and/or other vectored DSL system performance are realized through the use of UPBO parameters generated for a given residual FEXT environment.

UPBO for vectored DSL

Alien noise is removed from one or more receptor DSL lines after self-FEXT has been eliminated or reduced. Information about the alien noise in the form of slicer errors can be obtained from one or more donor DSL lines that may or may not be in the same domain (e.g., a vectored DSL system).

DSL alien noise reduction

A system for performing a single ended line test (SELT) of a selected subscriber line within a bundle of in-service subscriber lines each supporting frequency division multiplexed multi-tone modulated XDSL communications. The system comprises: a crosstalk cancellation module and a SELT module. The crosstalk cancellation module is coupled to the subscriber lines and configured to cancel crosstalk between the selected subscriber line under test and the in-service subscriber lines. The SELT module couples to the crosstalk cancellation module and is configured to coordinate SELT testing with the crosstalk cancellation module to cancel crosstalk between the selected subscriber line and the in-service subscriber lines during testing.

Method and apparatus for crosstalk cancellation during SELT testing

Growing community of inventors

Fremont, CA, United States of America

Shailendra Singh