Texas Instruments Corporation

Shailendra Kumar Baranwal

Yogesh Kumar Ramadass

Yinglai Xia

Junmin Jiang

Maurizio Granato

Giovanni Frattini

Anant Shankar Kamath

Jeffrey Anthony Morroni

Michael Lueders

Sujan Kundapur Manohar

William Todd Harrison

David Wayne Stout

Alan Stephen Bass

Amit Goyal

Abhijeeth Aarey Premanath

Abhijeeth A Premanath

Bhushan Talele

Giavanni Frattini

Vighnesh Rudra Das

A system includes a charge pump having an input coupled to a first voltage and an output at a second voltage, the second voltage greater than the first voltage. The system also includes an amplifier having a first input, a second input, and a third input, the first input coupled to the output of the charge pump, the second input coupled to the first voltage, the third input coupled to an input signal, the amplifier having an amplified output signal. The system also includes a maximum power detector coupled to the amplifier, the maximum power detector operable to determine whether the amplified output signal has reached a threshold output level and to reduce a power of the amplified output signal responsive to the determination.

Maximum power detection and automatic gain control for capacitive class-D amplifiers

Described embodiments include an audio amplifier circuit that includes a first amplifier having a differential first amplifier input adapted to be coupled to an audio input source, a multiplexer having first and second mux inputs, a control input and a mux output. The first mux input is coupled to the differential amplifier output. There is a signal generator having a generator input coupled to the mux output. There is also a driver circuit having a driver circuit input and a driver circuit output, the driver circuit input coupled to the generator output, and a second amplifier having a first error input coupled to a current sense terminal that is configured to provide a voltage proportional to a current supplied from a power supply terminal, and a second error input coupled to a current limit terminal configured to provide a reference voltage proportional to a current limit value.

Current limit for charge pump boost driven class D audio amplifier

A device includes a first ramp generator having a first ramp generator output configured to provide a first ramp, a second ramp generator having a second ramp generator output configured to provide a second ramp, and a third ramp generator having a third ramp generator output configured to provide a third ramp. The first ramp is a sawtooth voltage waveform having a first common mode voltage and a first peak-to-peak voltage. The second ramp is a sawtooth voltage waveform having a second common mode voltage and a second peak-to-peak voltage. The third ramp is a sawtooth voltage waveform having a third common mode voltage and a third peak-to-peak voltage. A frequency of the second ramp is approximately equal to a frequency of the third ramp, and the frequency of the third ramp is approximately double a frequency of the first ramp.

Folded ramp generator

In described examples, an isolated DC-DC converter includes: an input node for receiving an input voltage; a transformer including a primary side having first and second terminals and a primary side ground; and first and second low-side switches. The first low-side switch is coupled between the first terminal and the primary side ground. The second low-side switch is coupled between the second terminal and the primary side ground. A first voltage is across the first low-side switch, and a second voltage is across the second low-side switch. Also, the isolated DC-DC converter includes first and second high-side switches. The first high-side switch is coupled between the first terminal and the input node. The second high-side switch is coupled between the second terminal and the input node. Further, the isolated DC-DC converter includes a switch controller.

Isolated DC-DC converter

A system includes a high side transistor switch coupled to a first voltage node and a low side transistor switch coupled to the high side transistor switch at a switch node. The system further includes a unidirectional decoupling capacitor circuit including a capacitive component. The unidirectional decoupling capacitor circuit is coupled between the first voltage node and a common potential. Responsive to a voltage on the first voltage node being more than a threshold greater than an input voltage to the first voltage node, the unidirectional decoupling capacitor circuit is configured to sink current from the first voltage node to the capacitive component. The capacitive component can therefore be charged, with the charge used to subsequently power a load.

Unidirectional ring mitigation in a voltage converter

A multi-level ramp generator comprises three ramp generators. The first ramp generator generates a first ramp signal, comprising a sawtooth voltage waveform with a first common mode voltage and a first peak to peak voltage. The second ramp generator generates a second ramp signal, comprising a sawtooth voltage waveform with a second common mode voltage and a second peak-to-peak voltage. The third ramp generator generates a third ramp signal, comprising a sawtooth voltage waveform with a third common mode voltage and the second peak-to-peak voltage. The second and third ramp signals are in phase with each other and the first ramp signal is 180&#xb0; out of phase with the second and third ramp signals. In some implementations, each of the first, second, and third ramp generators comprise a respective delay locked loop and a respective voltage controlled oscillator.

Ramp generator for multilevel class-D amplifiers

An amplifier comprises eight transistors: the first coupled to a linked node and to a positive output node, the second coupled to the linked node and to a negative output node, the third coupled to the positive output node and a common potential, the fourth coupled to the negative output node and the common potential, the fifth coupled to a battery node, the sixth coupled to the fifth transistor and to the positive output node, the seventh coupled to the battery node, and the eighth coupled to the seventh transistor and to the negative output node. The amplifier also includes a charge pump to convert the battery voltage to an increased voltage on the linked node. The charge pump includes capacitors and operates at a lower frequency in lower power mode and a higher frequency in higher power mode to increase power provided to the linked node.

Multilevel class-D power stage including a capacitive charge pump

In described examples, an isolated DC-DC converter includes an input node for receiving an input voltage, and a transformer including a primary side having first and second terminals and a ground. First and second high-side switches are coupled between the input node and the first and second terminals, respectively. A first low-side switch is coupled between the first terminal and the ground, and through a first voltage limiter to be activated by a voltage at the second terminal. A second low-side switch is coupled between the second terminal and the ground, and through a second voltage limiter to be activated by a voltage at the first terminal. A switch controller controls the high-side switches so that voltages across the high-side switches are alternatingly zero, using a current through the primary side to alternatingly charge one terminal to an input voltage and discharge the other terminal to a ground voltage.

In described examples, an isolated DC-DC converter includes: an input node for receiving an input voltage; a transformer including first and second terminals; first and second low-side switches; and first and second high-side switches. The first low-side switch is coupled between the first terminal and a primary side ground. The second low-side switch is coupled between the second terminal and the primary side ground. The first high-side switch is coupled between the first terminal and the input node and is configured to be activated by a voltage at the second terminal. The second high-side switch is coupled between the second terminal and the input node and is configured to be activated by a voltage at the first terminal. Further, the isolated DC-DC converter includes a switch controller to cause the first and second voltages to alternatingly be zero by opening and closing the first and second low-side switches.

In an embodiment, an adaptive drive strength switching converter includes a driver and a control loop coupled to the driver. In an embodiment, the control loop includes a peak detector, a comparator coupled to an output of the peak detector, a counter coupled to an output of the comparator, and a digital-to-analog converter (DAC) coupled to an output of the comparator.

Adaptive drive strength switching converter

A bandgap voltage reference is provided in quasi-parallel with a resistor in the input path of a digital input circuit. Because of the quasi-parallel nature, the current used by the digital input circuit is limited to an amount based on the value of the external resistor. The input current is split between circuitry used to provide the logic signal across the selected isolation barrier and a sink transistor so that the current remains constant. This allows the digital input circuit to accurately limit input current without needing field-side power.

Input current limit in digital input receivers

An electronic device, which includes an H-bridge circuit and a miniaturized transformer that is coupled to operate at VHF frequency, and a driver circuit for an n-type power transistor of the H-bridge circuit are disclosed. The driver circuit includes a first p-type transistor and an n-type transistor coupled between an upper rail and a lower rail, with an output taken between the drains of the first p-type transistor and the n-type transistor being coupled to a gate of the n-type power transistor. The driver circuit also includes a sample-and-hold capacitor coupled to capture a drain voltage for the first n-type power transistor on a first edge of a control signal for the first n-type power transistor and a comparator coupled to compare the captured drain voltage to a lower rail on a given edge of a clock signal and to provide a comparator value. The driver circuit also includes an up/down counter, which is coupled to receive the comparator value, to adjust a counter value responsive to receiving the comparator value and to output the counter value, and a first timing circuit that is coupled to receive the counter value and to send an adjustable pulse towards a gate of the first p-type transistor and a gate of the n-type transistor.

Isolated high frequency DC/DC switching regulator

One example includes a switch circuit. The switch circuit includes a transistor configured to activate in response to an activation voltage at an activation terminal of the transistor. The switch circuit also includes a current source coupled to the activation terminal and being configured to generate an activation current. The switch circuit further includes a driver control circuit interconnecting the activation terminal and a voltage rail. The driver control circuit includes digital counter logic configured to cycle through a predetermined number of count values based on an oscillator signal. The driver control circuit is configured to adjust an amplitude of the activation voltage at each of the predetermined number of count values based on the activation current to provide a soft-start activation of the transistor.

Soft-start switch circuit

An LED input emulator to interface a signal source designed for use with an LED optocoupler, to capacitive or other galvanic isolation circuitry, emulating LED forward and reverse bias voltages. VR reverse blocking circuitry includes MPand MPPMOS transistors coupled to an emulator anode port, and to emulate LED reverse bias voltage. VF control circuitry includes a variable resistance (MP) coupled between anode and cathode ports, and a current control circuit coupled to an output node, and to control current through the variable resistance to maintain a desired forward voltage at the output node. In an example embodiment, the VF control circuitry is implemented with an amplifier and a bandgap voltage reference circuit coupled to the output node, generating both reference and feedback voltages input to the amplifier to control the variable resistance.

Growing community of inventors

Murphy, TX, United States of America

Shailendra Kumar Baranwal