Chameleon Systems, Inc.

Intel Corporation

Shaila Hanrahan

Christopher E Phillips

Peter Shing Fai Lam

Simon Guo

A floorplan for a reconfigurable chip uses slices adjacent to each of four corners of a region, each of the slices including tiles that contain multiple reconfigurable functional units including ALUs. The placement of the slices in the corners of their region allows for better and quicker interconnection between elements on the slices.

Faster scalable floorplan which enables easier data control flow

A reconfigurable chip having reconfigurable elements uses an interconnection system which reduces the maximum signal rise and fall time. In one embodiment, the maximum rise and fall time is reduced by providing bypass paths. In another embodiment, buffers are used to reduce signal rise and fall times. Connections between each of the elements are provided by either providing a loop path or by providing bidirectional arrangements of the buffers.

Data transfer on reconfigurable chip

A reconfigurable chip includes data registers which can be loaded from off-chip or on-chip. The data register comprises a register block produced from a number of register block units. The register bock units include an active plane store storing the current value of the register bit, at least one off-chip data background store storing a data bit which can be loaded from off-chip, and at least one on-chip data background store storing a value which can be loaded from on-chip.

Loading data plane on reconfigurable chip

A reconfigurable system is arranged to have separate control and the data paths. The control path is set up using control fabric units which use an associated state machine to produce an address to a functional unit memory. The functional unit memory then produces the configuration data for the functional units. The use of a state machine allows for a very dense, highly-sequencable control unit that provides an encoded state to a memory which then allows a high number of control terms which results in a more linear interconnection to the data path units.

Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit

A reconfigurable programmable sum of products generator allows for multiple configurations to be associated with a programmable sum of products generator. These configurations can be modified by changing the configurations in an associated configuration memory for the programmable sum of products generator. By using a reconfigurable programmable sum of products generator structure, a dense and highly interconnected logic is produced. Such a dense and highly interconnected logic is particularly valuable for use in the control path of a reconfigurable system.

Reconfigurable program sum of products generator

A configuration state memory is associated with a configurable functional block on a reconfigurable chip. The configuration state memory stores more than one configuration for the functional block. This allows the functional block to switch configurations without requiring the configuration data to be loaded from off-chip which would stall the operation of the reconfigurable chip. In a preferred embodiment, the configuration state memory uses a relatively few address bits to produce a relatively broad configuration output to the functional blocks. The small number of input address bits allows the configuration state memory to be addressed by relatively small state machine unit.

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San Jose, CA, United States of America

Shaila Hanrahan