Freescale Semiconductor,inc.

Motorola Corporation

Nxp Usa, Inc.

Shai Shperber

Yoav Weizman

Ezra Baruch

Lior Aviv

Jacob Fridburg

Rinatya Levy

Dmitri Akselrod

A semiconductor device arrangement comprising a functional circuit comprising a plurality of timing components and a reference module comprising a plurality of reference components is described. Each reference component comprises a reference timing component corresponding to a timing component of the plurality of timing components and a controllable timing component. The controllable timing component is arranged to provide a delay in dependence on an applied light stimulus. A method of analyzing a performance of a functional circuit on a semiconductor device is also described. A device analysis system for analyzing a functional circuit comprising a plurality of timing components is also described.

Semiconductor device arrangement, a method of analysing a performance of a functional circuit on a semiconductor device and a device analysis system

An on-die capacitance measurement module (ODCMM) arranged to measure a capacitance element. The ODCMM comprises an oscillating voltage supply that outputs first and second oscillating voltage signals, the first and second oscillating voltage signals comprising differing phases, and the oscillating voltage supply component coupled to a first node of the capacitance element and arranged to provide thereto the first oscillating voltage signal, and a reference voltage component coupled to a second node of the capacitance element to provide a reference voltage signal. The ODCMM operates in a first mode, wherein the reference voltage component is arranged to provide a constant reference voltage to the second node of the capacitance element. The ODCMM is arranged to operate in a second mode, wherein the reference voltage component is arranged to provide a reference voltage signal representative of the second oscillating voltage signal output by the oscillating voltage supply component to the second node of the capacitance element.

On-die capacitance measurement module and method for measuring an on-die capacitive load

A method for evaluating temperature is disclosed. The method includes setting a configuration of a configurable delay line out of multiple possible configurations, and delaying a first input signal by a temperature sensitive delay line, delaying a second input signal by the configurable delay line. The configurable delay line is less sensitive to temperature than the temperature sensitive delay line. The method also includes detecting, by a phase detector, a delay difference between a delay introduced by the temperature sensitive delay line and a delay introduced by the configurable delay line, repeating the setting, delaying of the first input signal, delaying of the second input signal and detecting, until the delay difference is below a threshold, and evaluating the temperature of the temperature sensitive delay line in response to a configuration of the configurable delay line that results in the delay difference that is below the threshold.

Device and method for evaluating a temperature

A device having temperature evaluating capabilities, the device includes: (i) a temperature sensitive delay line that comprises multiple first type NMOS transistors and first type PMOS transistors; (ii) an configurable delay line that comprises second type NMOS transistors and second type PMOS transistors; wherein a process condition sensitivity of first type NMOS transistors and first type PMOS transistors substantially equals a process condition sensitivity of the second type NMOS transistors and second type PMOS transistors; wherein the configurable delay line is less sensitive to temperature than the temperature sensitive delay line; (iii) a phase detector, coupled to an output of the temperature sensitive delay line and to an output of the adjustable delay line, the phase detector is adapted to determine a difference between a delay introduced by the temperature sensitive delay line and a delay introduced by the adjustable delay line; and (iv) a controller, adapted to: (a) find a configuration of the configurable delay line that introduces a delay that substantially equals a delay introduced by the temperature sensitive delay line; and (b) determine a temperature of the temperature sensitive delay line in response to the found configuration.

A system () for testing and failure analysis of an integrated circuit () is provided using failure analysis tools (). An analysis module () having a number of submodule test structures is incorporated into the integrated circuit design. The test structures are chosen in dependence upon the failure analysis tools () to be used. The rest of the integrated circuit contains function modules () arranged to provide normal operating functions. By analysing the submodule test structures of the analysis module () using the failure analysis tools (), physical parameters of the integrated circuit () are obtained and used in subsequent testing of the function modules () by the failure analysis tools (), thus simplifying the testing of the integrated circuit () and reducing the time taken to perform a failure analysis procedure.

Analysis module, integrated circuit, system and method for testing an integrated circuit

A device and a method for patching code residing on a ROM module, the device comprising a patch detect logic and a patch translation logic, the method comprising the steps of: (I) providing a set of M fields, each field indicating a validity of a content of a GROUP of at least two memory words stored in the ROM module. (II) receiving a request to provide a content of a requested memory portion located at an ADDRESS within the ROM module, the requested memory word being a part of a requested GROUP, the requested GROUP is associated to a selected field out of the M fields. (III) fetching a selected field associated to the requested memory portion. (IV) checking the selected field and accordingly either (a) providing a patched code if the selected field indicates that the requested GROUP is not valid; else (b) providing a content of the requested memory portion.

DEVICE AND METHOD FOR PATCHING CODE RESIDING ON A READ ONLY MEMORY MODULE UTILIZING A RANDOM ACCESS MEMORY FOR STORING A SET OF FIELDS, EACH FIELD INDICATING VALIDITY OF CONTENT OF A GROUP, AND FOR RECEIVING AN ADDRESS OF A MEMORY PORTION OF THE READ ONLY MEMORY

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Bat Hefer, Israel

Shai Shperber