Lsi Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Shai Kalfon

Ido Gazit

Eran Goldstein

Moshe Bukris

Assaf Prihed

Alexander Rabinovitch

Sharon Rosenschein

Assaf Pihed

Yair Amitay

In described embodiments, a physical downlink control channel of a device operating in accordance with a 3GPP LTE standard is processed to provide interleaving, modulation and multi-layer mapping and pre-coding. A Resource Element Group interleaver applies interleaving to an input signal representing an input bitstream, and a modulator modulates the input signal. After interleaving and modulating the signal, a multi-layer mapper and pre-coder layer-maps and pre-codes the interleaved and modulated input signal into a plurality of different layers.

Interleaving, modulation, and layer mapping in an LTE physical control channel

A transmitter comprises indicator channel processing circuitry configured to process indicator channel codewords for transmission in a base station of a wireless system. The indicator channel processing circuitry performs a plurality of processing operations on the indicator channel codewords in a specified processing sequence, with the plurality of processing operations comprising at least modulation, scrambling, spreading and combining. In the specified processing sequence, the scrambling operation is performed for at least a given one of the indicator channel codewords prior to the modulation and spreading operations for that codeword or subsequent to the combining operation for that codeword. For example, the specified processing sequence may comprise the scrambling, modulation, spreading and combining operations performed in that order for at least the given codeword, or the modulation, spreading, combining and scrambling operations performed in that order for at least the given codeword.

Downlink indicator channel processing in a wireless system base station

An apparatus having a database and a circuit is disclosed. The database may be configured to store a plurality of entries. The circuit may be configured to (i) insert a plurality of indicators into a frame, (ii) generate the entries in the database and (iii) transmit the frame in response to the entries such that power is applied to an antenna corresponding to each of a plurality of data items in the frame and no power is applied to the antenna corresponding to each of the indicators in the frame. Each of the entries generally identifies a respective location in the frame. Each of the locations may begin a respective string comprising at least one of the indicators.

Discontinuous transmission in a frame

A transmitter comprises resource mapping circuitry configured to map symbols from multiple control channels to transmission symbols in a base station of a wireless system. The resource mapping circuitry comprises a table-based mapper configured to receive the control channel symbols and to map those symbols to the transmission symbols utilizing at least a selected one of a plurality of tables providing respective distinct mappings between the control channel symbols and the transmission symbols. For example, each of the transmission symbols may comprise a plurality of resource groups and the tables may specify distinct mappings of the control channels symbols to resource groups for different sets of possible base station parameter values. In one embodiment, the control channels comprise a physical control format indicator channel (PCFICH), a physical downlink control channel (PDCCH), and a physical hybrid ARQ indicator channel (PHICH) of an LTE cellular system.

Table-based resource mapping for downlink control channels in a wireless system base station

An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate pseudo-random sequences in response to a first m-sequence and a second m-sequence, where the first m-sequence is initialized with a pre-calculated constant and the second m-sequence is initialized based on a pre-defined initial sequence and a table of pre-calculated values indicating which components of the initial sequence participate in initializing the second m-sequence. The second circuit may be configured to store the table of pre-calculated values.

Method for fast calculation of the beginning of pseudo random sequences for long term evolution

An apparatus comprising a decoder circuit and a memory. The decoder circuit may be configured to generate a single address signal to read a first parity data signal, a second parity data signal and read and/or write systematic information data, a first a-priori-information signal and a second a-priori-information signal. The decoder circuit (i) reads the first parity data signal, the systematic information data and the first a-priori-information during even half-iterations of a decoding operation and (ii) reads the second parity data, the systematic information data and the second a-priori-information during odd half-iterations of the decoding operation. The memory may be configured to store the systematic information data and the first and second a-priori-information signals such that each are accessible by the single address signal.

Multi-processing architecture for an LTE turbo decoder (TD)

An apparatus including a processor and a radio frequency (RF) interface. The processor may be configured to process downlink information such that a latency of the apparatus is determined by an amount of time involved in processing the downlink information to obtain a single orthogonal frequency division multiplexed (OFDM) symbol for presentation to the RF interface.

Method for reducing latency on LTE DL implementation

Described embodiments provide a wideband code division multiple access (W-CDMA) system that employs a rate matching rule having a modified puncturing algorithm. The modified puncturing algorithm defines the input variables of the rate matching rule in a manner that provides for identification of relations between non-punctured data bit position addresses in the output data stream through an iterative process, from which absolute bit position addresses of non-punctured output bits might then be generated. A counter, in accordance with instruction generated by a processor or state machine, for example, might implement the modified puncturing algorithm on an input string of bits to provide an output string of bits based on the absolute bit position addresses of non-punctured output bits, thereby providing for rate matching in the communications channel.

Rate matching for wideband code division multiple access

Described embodiments provide a wireless communication system that employs modulation and precoding. An input bit stream is divided into one or more batches. Each batch has a consecutive number of bits. A modulation scheme is determined for batches. A precoding scheme for layer mapping is determined for the batches. Based on the modulation scheme and precoding scheme, a look-up table (LUT) is selected. The selected LUT maps the batches into one or more modulated and precoded layers. The modulated and precoded batches are provided to a transmission module.

Modulation and layer mapping in physical channels

An iterative PCCC encoder includes a first delay line operative to receive at least one input data sample and to generate a plurality of delayed samples as a function of the input data sample. The encoder further includes a second delay line including a plurality of delay elements connected in a series configuration. An input of a first one of the delay elements is adapted to receive a sum of first and second signals, the first signal generated as a sum of the input data sample and at least one of the delayed samples, and the second signal generated as an output of a single one of the delay elements. A third delay line in the encoder is operative to generate an output data sample as a function of the sum of the first and second signals and a delayed version of the sum of the first and second signals.

Turbo parallel concatenated convolutional code implementation on multiple-issue processor cores

An apparatus including a processor, a computer readable storage medium, and a lookup memory. The computer readable storage medium generally contains computer executable instruction that when executed by the processor perform operations involving fixed point multiplication. The lookup memory generally stores values used in the fixed point multiplication. The values stored in the lookup memory are approximated based upon a predetermined value to prevent overflow in the fixed point multiplication.

Method for avoiding overflow of multiplication of roots-of-unity by using overflow safe approximated values table

Described embodiments provide a wideband code division multiple access (W-CDMA) system, that employs an interleaving rule having a modified pruning algorithm. Interleaving, by pruning a sequence of bits in the W-CDMA system, includes determining a non-pruned interleaved vector having a length N. The determination of the non-pruned interleaved vector is based on a received length of an input vector from the sequence of bits. The input vector is padded. An interleaver generates a pre-pruned interleaved vector having a length equal to the length N, wherein the pre-pruned interleaved vector is a function of the padded input vector and the non-pruned interleaving vector. The interleaver prunes one or more elements from the pre-pruned interleaved vector based on a corresponding pruning indication in a pruning indication table, thereby providing a pruned interleaved vector as a portion of the interleaved sequence of bits.

Interleaving for wideband code division multiple access

An apparatus including a first circuit and a second circuit. The first circuit may be configured to store a block of data values arranged in a first order. The first circuit may be further configured to present a plurality of the data values in parallel in response to a plurality of address signals, where the data values are presented in a second order. The second circuit may be configured to generate the plurality of address signals in response to a first signal, a second signal and a third signal. The second circuit generally includes an even number of address generators configured to generate the plurality of address signals in parallel.

Simplified parallel address-generation for interleaver

An apparatus generally having a lookup table and a circuit is disclosed. The lookup table may be configured to store a plurality of results including remainders of divisions by a particular polynomial. The circuit may be configured to (i) parse a first polynomial into a plurality of data blocks and an end block, (ii) fetch a plurality of results from the lookup table by indexing the lookup table with each of the data blocks and (iii) generate a second polynomial by adding the results fetched from the lookup table to the end block. The second polynomial generally has a second degree that is lower that a first degree of the first polynomial.

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Hod Hasharon, Israel

Shai Kalfon