Proteantecs Ltd.

Mellanox Technologies, Ltd.

Shai Cohen

Evelyn Landman

Eyal Fayneh

Inbar Weintrob

Yahel David

Guy Redler

Yair Talker

Shmuel Levy

Elad Mentovich

Sylvie Rockman

Eyal Moshe Waldman

Liron Gantz

Benny Koren

Jacob Levy

Hananel Faig

Johan Jacob Mohr

Shai Rephaeli

Ran Sela

Aviv Berg

Eyal Babish

Eyal David

Beeri Halachmi

Stanislav Gurtovoy

Alex Khazin

Ronnen Lovinger

Daniel Kedar

Segev Zarkovsky

Idan Yokev

Alexander Burlak

Edi Shmueli

Alexander Kaminsky

Amihai Moshe Kopel

A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.

Integrated circuit profiling and anomaly detection

A semiconductor integrated circuit (IC) comprising a time-to-digital converter (TDC) configured to measure an input-to-output delay of an I/O buffer of a pad the IC, the measured delay reflecting a connection impedance of the pad. A circuit in the IC, or a computer in communication with the IC, determines electrical connection integrity of the pad based on the measured delay of the I/O buffer.

Integrated circuit pad failure detection

A system includes a memory device and a processing device, operatively coupled to the memory device, to perform operations including receiving, from a thermal sensor group including thermal sensors, hotspot temperature measurements with respect to a hotspot. Each temperature measurement is received from a respective thermal sensor. The operations further include determining, from the temperature measurements, a generalized hotspot temperature measurement for the thermal sensor group.

Thermal sensor integration for system temperature management

Structural testing of a semiconductor integrated circuit (IC), including scanning test patterns or test conditions into internal circuits of the semiconductor IC, for example from a tester device. A timing margin may be measured during the structural test. The margin is measured based on a characteristic of a comparison between a test signal path of the semiconductor IC and a delayed signal path, the delayed signal path being a signal of the test signal path delayed by a variable delay time. An output of the margin measurement sensor may be scanned out, for instance to the tester device.

Integrated circuit margin measurement for structural testing

A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.

Efficient integrated circuit simulation and testing

Loopback testing may be provided for one or more transmission output paths of a semiconductor Integrated Circuit (IC). One or more parametric loopback sensors are provided in the semiconductor IC, each parametric loopback sensor being configured to receive a clocked data input signal to a respective transmitter of the IC and a signal from a transmission output path from the respective transmitter of the IC, and to generate a respective sensor output based on a comparison of the clocked data input signal and the signal from the transmission output path for the respective transmitter of the IC. A programmable load circuit is also provided in the semiconductor IC, coupled to each transmission output path.

Loopback testing of integrated circuits

An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.

Integrated circuit workload, temperature, and/or sub-threshold leakage sensor

A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.

Integrated circuit margin measurement and failure prediction device

An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.

Integrated circuit I/O integrity and degradation monitoring

Integrated circuit degradation estimation and time-of-failure prediction using workload and margin sensing

A polarization recovery device comprises an input that receives a first optical signal with unknown polarization and with at least one signal parameter at an initial value, a first output that outputs a second optical signal with known polarization and with the at least one signal parameter at or near the initial value, and a recovery block that generates the second optical signal based on the first optical signal.

Systems, devices, and methods for polarization recovery

Determination of one or more operating conditions (leakage current, temperature and/or workload) of a functional transistor in a semiconductor integrated circuit (IC). The functional transistor provides an electrical current, which is provided as an input to a ring oscillator (ROSC). The ROSC is located in the IC proximate to the functional transistor and has an oscillation frequency in operation. The one or more operating conditions of the functional transistor are determined based on the oscillation frequency of the ROSC.

Integrated circuit workload, temperature and/or subthreshold leakage sensor

A semiconductor integrated circuit (IC) comprising a time-to-digital converter circuit (TDC), wherein time inputs to the TDC are (i) one or more input to an input/output (I/O) buffer of a pad of the IC, and (ii) one or more output from the I/O buffer. The IC comprises a digital comparator circuit electrically configured to: receive a stream of digital output values from the TDC, compare each value of the stream to one or more previous value in the stream, and when the comparison reflects a difference value greater than a threshold, issuing a notification to a user of the IC.

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Haifa, Israel

Shai Cohen