Agere Systems Inc.

Lsi Corporation

Agere Systems Guardian Corp.

Shahriar Moinian

Debra Sharon Johnson

Shye Shapira

Seung Hyuk Kang

Yi Ma

Ya-Hong Xie

William Burdett Wilson

Chung Wai Leung

William Thomas Cochran

Kenneth Wade Paist

Yih-Feng Chyan

James D Chlipala

Chunchieh Huang

Weiwei Mao

Nathan R Belk

Mark Richard Pinto

Kwok K Ng

Michel Ranjit Frei

Chi-Yi Kao

John E Scoggins

John Jansen

David Clayton Goldthorp

John Anthony Pantone

Shawn Boshart

Joshua Williams

Kausar Banoo

Blane A Musser

Hong-Ha Vuong

Ce Chen

A parameterizable design system is for use with semiconductor analog circuits and includes an interface unit connected to provide access to the system, a database unit connected to supply a library of parameterizable analog building blocks for a design entity, and a parameterization unit connected to select a parameter for one of the library of parameterizable analog building blocks to meet a design specification of the design entity. Additionally, the parameterizable design system may also include a simulation unit connected to simulate an operation of the design entity employing the parameter, and an analyzer unit connected to analyze a sensitivity of the parameter for the design entity based on the design specification. A method of designing a semiconductor analog circuit is also included.

Fully parameterizable representation of a higher level design entity

An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization level located over the active layer that provides logic interconnects and metal capacitor plates. The logic interconnects are connected to the logic circuit and the metal capacitor plates are connected to the eDRAM cell. The electronic device additionally includes a second metallization level located over the first metallization level that provides an interconnect connected to at least one of the logic interconnects, and a bit line that is connected to the eDRAM cell. A method of manufacturing an electronic device is also included.

Logic-based eDRAM using local interconnects to reduce impact of extension contact parasitics

An IC inductor structure is provided which includes a first inductor element formed on a semiconductor substrate and at least a second inductor element formed on the semiconductor substrate proximate the first inductor element. The first inductor element has a first effective magnetic field direction associated therewith, and the second inductor element has a second effective magnetic field direction associated therewith. The first and second inductor elements are oriented relative to one another so as to create a non-zero angle between the first and second effective magnetic field directions.

Integrated circuit inductors with reduced magnetic coupling

An inductor device in an integrated circuit includes a first winding portion, a bridge portion and a second winding portion. The integrated circuit has a first, a second, a third and a fourth metallization level. The first winding portion comprises a first metal line formed on the first metallization level and a second metal line formed on the second metallization level, the first metal line being electrically connected in parallel with the second metal line. The bridge portion comprises a third metal line formed on the third metallization level and a fourth metal line formed on the fourth metallization level, the third metal line being electrically connected in parallel with the fourth metal line. The second winding portion comprises a fifth metal line formed on the first metallization level and a sixth metal line formed on the second metallization level, the fifth metal line being electrically connected in parallel with the sixth metal line. The bridge portion electrically connects the first winding portion to the second winding portion.

Differential inductor for use in integrated circuits

Techniques are presented for reliability analysis of integrated circuits. A circuit data file including a connectivity network with appended parasitic information is obtained. Circuit performance is simulated, based on the data file, to obtain simulated currents for metallic conductive paths of the circuit. Contextual representations of the paths are determined, and reliability analysis is performed on the contextual representations. The analysis can relate, for example, to electromigration, joule-heating, and/or fusing. The results of the analysis can be provided, for example, in the form of a report including recommended changes, such as width increases, to wires for which it is determined that reliability issues exist.

Reliability analysis of integrated circuits

The present invention provides an varactor, a method of manufacture thereof. In an exemplary embodiment, the varactor includes a semiconductor substrate and well of a first and second conductivity type, respectively. A conductive region in the well has a same conductivity type as the well but a lower resistivity than the well. At least a portion of the well is between at least two sides of the conductive region and an area delineated by an outer perimeter of a conductive layer over the well. Such varactors have a lower series resistance and therefore have an increased quality factor.

Increased quality factor of a varactor in an integrated circuit via a high conductive region in a well

The present invention provides a method for manufacturing a semiconductor device, comprising: determining an isolation structure stress effect of a first semiconductor device, determining an optical proximity effect of a second semiconductor device, selecting a modeling design parameter such that the isolation structure stress effect is offset against the optical proximity effect on a fabrication model, and using the selected design parameter to construct a third semiconductor device.

Method of making a semiconductor device by balancing shallow trench isolation stress and optical proximity effects

The present invention provides a bipolar transistor located on a semiconductor wafer substrate. The bipolar transistor may comprise a collector located in the semiconductor wafer substrate, a base located in the collector, and an emitter located on the base and in contact with at least a portion of the base, wherein the emitter has a low K layer located therein. The low K layer may be, for example, located proximate a side of the emitter, or it may be located proximate opposing sides of the emitter. In all embodiments, however, the low K layer does not interfere with the proper functioning of the bipolar transistor, and substantially reduces the emitter-base capacitance typically associated with conventional bipolar transistors.

Bipolar transistor with a low K material in emitter base spacer regions

An integrated circuit with a buried layer for increasing the Q of an inductor formed in the integrated circuit. The substrate includes a highly doped buried preserving device and latchup characteristics. The inductor may also include an increased thickness conductive layer in the inductor to further increase Q. The present invention is also directed to a low loss interconnect.

Inductor or low loss interconnect and a method of manufacturing an inductor or low loss interconnect in an integrated circuit

Growing community of inventors

New Providence, NJ, United States of America

Shahriar Moinian