International Business Machines Corporation

Shahram Salamian

Brian Walter O'Krafka

Jace W Krull

Nadeem Malik

Jeffrey Thomas Kreulen

Avijit Saha

Charles Edward Kuhlmann

Sriram Srinivasan Mandyam

Robert F Kantner, Jr

Ramanathan Raghavan

James T Tsevdos

Carl Henry Grant

Eugene M Thomas

Tze-Wing Keung

A method and apparatus for creating a multiprocessor verification environment. A Multiprocessor Test Generator (MPTG) generates a set of test cases in a Multiprocessor Test Language (MTL) format subject to constraints and enumeration controls in a test specification. An abstract system model of the machine under test is inputted to the Multiprocessor Test Generator. The Multiprocessor Test Generator (MPTG) receives the test specification and abstract system model, accesses a system specific database and generates test cases based on the constraints in the test specification in a Multiprocessor Test Language (MTL). The Multiprocessor Test Language (MTL) test cases are inputted to a Multiprocessor Test Executive (MPX) which controls the issuance of the test cases to a cache-coherent multiprocessor system, and monitors their completion in order to verify operation of the cache-coherent multiprocessor system.

Method and apparatus for creating a multiprocessor verification

A method and system are disclosed for verifying consistency of an instruction execution order of a multiprocessor data processing system with a specified memory consistency model. Each processor within the multiprocessor data processing system executes instructions from an associated one of a number of instruction streams, which include instructions that store a number of unique values from multiple processors to a single selected address within memory. One of the unique values is loaded from the selected address to a particular processor within the data processing system. A set of valid values which may be returned by the loading step is determined according to the specified memory consistency model. By comparing the unique value with members of the set of valid values, the instruction execution order of the multiprocessor data processing system is verified. Utilizing the unique value which was returned by the load instruction, the set of valid values may then be updated.

Method and system for verifying execution order within a multiprocessor

A computer system is provided in which asynchronously operating processing elements in the system are connected by means of an interconnection media so as to permit communication between an executing program on one of the processing elements with the memory on another processing element. Inter-processing communication logic located on each of the processing elements permits communication between executing programs on any one processing element. Inter-delivery support hardware is provided for interfacing between the interconnection media and the inter-processing communication logic. The inter-delivery support hardware operates asynchronously with respect to the executing programs on the processing elements for (i) enqueuing control elements obtained by a function on a first processing element from physical memory on the first processing element; (ii) temporarily storing the enqueued control elements in a first memory device associated with the first processing element; (iii) copying over the interconnection media via a copy transaction the temporarily stored control elements from the first memory device to a second memory device associated with a second processing element; and (iv) dequeuing the copied control elements from the second memory device to physical memory on the second processing element.

Method and apparatus for distributing control messages between

A data communication system contains a dual-port/dual-access-mode storage subsystem, and a communication controller connecting between that subsystem and external data communication channels. The storage subsystem includes one or more dual-port/dual-access mode storage devices consisting of a pair of random access and sequential access memory arrays, with a parallel block transfer connection between the arrays. The sequential access array can store a large block of up to N bytes (N for example equal to 256), and the random access array can store multiple such blocks. The subsystem also has RAM and SAM access ports respectively controllable in random access and sequential access modes and respectively connecting to the random access and sequential access arrays. In random access mode a group of from 1 to 4 bytes is transferred between the controller and a specified address in the random access array, and in sequential access mode a block of up to N bytes is transferred in a sequential manner between the controller and the sequential access array and in a parallel manner between that array and a discretely addressed block of space in the random access array. Transfers of relatively long and short data communication messages are routed respectively through the SAM and RAM external ports by the controller, so as to efficiently match bandwidth requirements of external communication channels with access characteristics of the RAM and SAM ports.

Use of video RAM in high speed data communications

Growing community of inventors

Austin, TX, United States of America

Shahram Salamian