Intel Corporation

Shahram Jamshidi

Sudarshan Kumar

Feng Chen

Thomas D Fletcher

Zhanping Chen

Sadhana Madhyastha

Kin Yip Sit

Lakshman Thiruvenkatachari

Sadarshan Kumar

Some embodiments provide dynamic circuits with dynamic nodes that may float during a disable mode to reduce leakage.

Domino circuit with disable feature

Although there are a number of techniques available to reduce leakage current, there is still considerable room for improvement. Accordingly, the present inventors devised, among other things, an exemplary method which entails defining first and second leakage-reduction vectors for respective first and second portions of an integrated circuit, such as a microprocessor. The leakage-reduction vectors, in some embodiments, set the first and second portion to minimum leakage states and thus promise to reduce leakage power and extend battery life in devices that incorporate this technology.

Leakage control in integrated circuits

A gate-clocked domino circuit with reduced leakage current during an inactive state, where domino stages in the domino circuit have long channel length transistors in the pre-charge paths. During an inactive state, the domino stages are put in an evaluation state and are discharged.

Gate-clocked domino circuits with reduced leakage current

A memory, such as a register file or a cache, having stack pMOSFETs shared among its word line drivers, where a stack pMOSFET shared by a set of word line drivers has its drain connected to the sources of the pMOSFETs in the set or word line drivers, and were each stack pMOSFET is controlled by an enable signal so as to turn ON only if its corresponding set of word line drivers is enabled. The enable signal may be provided by a write or read enable port, or by the memory's address decoder. The stacked configuration of pMOSFETs significantly reduces sub-threshold leakage current in the word line drivers with very little penalty in performance.

Word line transistor stacking for leakage control

A small swing reducer circuit. An apparatus includes a first number of input terminals including at least two input terminals coupled to receive a differential small swing signal and a reducer circuit to generate differential, small swing sum and carry output signals based on data received via the input terminals.

Differential, low voltage swing reducer

An entry latch to provide a dynamic signal at an output port in response to input static signals at a pulldown network, the pulldown network to conditionally discharge an internal node depending upon the input static signals, the entry latch comprising a pass transistor having a first source/drain connected to the output port and a second source/drain connected to a gate of a pullup pMOSFET, where the pullup pMOSFET turns ON only if the pulldown network does not turn ON during the evaluation phase.

Low power entry latch to interface static logic with dynamic logic

A multiplexing arrangement. The multiplexing arrangement comprises a set of data inputs wherein a first multiplexer is coupled to a first subset of the set of data inputs and a second multiplexer is coupled to a second subset of the set of data inputs. Only one of the first and second multiplexers is selected to pass one of the set of data inputs at any given time. A logic gate is coupled to the first and second data outputs, and the logic gate synthesizes an output signal for the multiplexing arrangement in response to values output by the first and second multiplexers such that the multiplexing arrangement operates as a single multiplexer. According to one embodiment, the multiplexer that is not selected to pass data has its output biased to a known state.

Plurality of distinct multiplexers that operate as a single multiplexer

A multiplexer. The multiplexer comprises a first data input and a second data input coupled to a logic gate via a first data path and a second data path, respectively, wherein a maximum of one of the first and second data paths is enabled to pass data at any given time. The data paths are independent of one another such that devices of the first data path do not load the second data path, and vice versa. The speed of a data path is determined by how many data input signals are routed through the same data path. In this manner, the speed of each data path may be tuned as required to provide the necessary operating speeds.

Multiplexer having a plurality of internal data paths that operate at

A multiplexer that comprises a first input buffer and a first pass gate coupled in series between a first data input and a common node and a second input buffer and a second pass gate coupled in series between a second data input and the common node. A biasing circuit is coupled to the common node and a supply voltage to bias the common node to the supply voltage when neither pass gate is switched on to pass data from its corresponding input buffer to the common node. An output buffer is coupled to the common node for outputting an output signal to a data output in response to a voltage of the common node.

Growing community of inventors

Cupertino, CA, United States of America

Shahram Jamshidi