Cypress Semiconductor Corporation

Shahin Sharifzadeh

Ravindra Manohar Kapre

Krishnaswamy Ramkumar

Helmut Puchner

Gabriel M Li

Sundar Narayanan

Bo Jin

Jianmin Qiao

K Nirmal Ratnakumar

Kenelm G D Murray

Ahmad Chatila

Jose Arreola

Kuantai Yeh

Nayan Patel

Ravlndra Kapre

A memory including current-limiting devices and methods of operating the same to prevent a spread of soft errors along rows in an array of memory cells in the memory are provided. In one embodiment, the method begins with providing a memory comprising an array of a plurality of memory cells arranged in rows and columns, wherein each of the columns is coupled to a supply voltage through one of a plurality of current-limiting devices, Next, each of the plurality of current-limiting devices are configured to limit current through each of the columns so that current through a memory cell in a row of the column due to a soft error rate event does not result in a lateral spread of soft errors to memory cells in the row in an adjacent column. Other embodiments are also provided.

Memory cell array latchup prevention

A current-limiting device may be configured to be placed along a power-supply bus to limit current through a first complimentary-metal-oxide semiconductor (CMOS) circuit coupled to the power-supply bus so that current does not exceed a trigger current level of a pnpn diode in a second CMOS circuit coupled to the power bus.

An embodiment includes configuring a current-limiting device to place along a power-supply bus to limit current through a first complimentary-metal-oxide semiconductor (CMOS) circuit coupled to the power-supply bus so that current does not exceed a trigger current level of a pnpn diode in a second CMOS circuit coupled to the power bus.

A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level.

Memory cell array

A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit. The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level.

In an embodiment of an integrated circuit structure having buried layer substrate isolation and a method for forming same, a buried layer having conductivity type opposite to that of an overlying well region is used for wells containing transistors prone to noise generation, where the wells are of the same conductivity type as the substrate. The buried layer may in some embodiments include a first portion underlying the transistor and a second portion spaced apart from and laterally surrounding the first portion. In some embodiments, the circuit may include a doped annular region of the same conductivity type as the buried layer, where the annular region contacts a portion of the buried layer and laterally surrounds the transistor. The circuit may further include metallization adapted to connect the well and annular region to opposite polarities of a power supply voltage, or in some embodiments to preclude such connection.

Buried layer substrate isolation in integrated circuits

In one embodiment, a transistor is fabricated by forming gate materials, such as a gate oxide layer and a gate polysilicon layer, prior to forming a shallow trench isolation (STI) structure. Forming the gate materials early in the process minimizes exposure of the STI structure to processing steps that may expose its corners. Also, to minimize cross-diffusion of dopants and to help lower gate resistance, a metal stack comprising a barrier layer and a metal layer may be employed as a conductive line between gates. In one embodiment, the metal stack comprises a barrier layer of tungsten-nitride and a metal layer of tungsten.

Formation of a shallow trench isolation structure in integrated circuits

According to one embodiment ( ), a method of forming a self-aligned contact can include forming adjacent conducting structures with sidewalls ( ). A first insulating layer may then be formed without first forming a liner ( ), such as a liner that is conventionally formed to protect underlying conducting structures and/or a substrate. A contact hole may then be etched between adjacent conducting structures ( ). Contact structures may then be formed ( ).

Semiconductor structure and method of making contacts in a semiconductor structure

The present invention concerns a process that maintains a second (or 'replica') set of alignment marks during existing processing steps used in manufacturing a semiconductor device or integrated circuit, including CMP and other planarization methods. The present invention avoids alignment problems encountered in conventional CMP processes, particularly tungsten CMP. All alignment steps can be realized through one or more subsequent second (or 'replica') alignment marks, set and preserved throughout the remaining process steps, thus maintaining alignment integrity. The present method and apparatus concerns a new alignment mark that may be 'printed' in a metal layer on the wafer, for example, a local interconnect or contact layer. The new alignment mark is generally not subjected to planarization or to an 'open frame' process. The new alignment mark may also be used to re-etch other alignment marks directly onto the layer conventionally causing alignment problems, such as those created following CMP.

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Menlo Park, CA, United States of America

Shahin Sharifzadeh