Codex Corporation

Shahid U Qureshi

Fuyun Ling

George D Forney, Jr

George P Chamberlin

Yosef Linde

Robert M Wilson

Karl W Seitz

Apparatus for enabling a first processor to cause a second processor to effect a transfer of data between the processors in accordance with data transfer commands sent from the first processor to the second processor is described. The processors each have a program instruction memory for enabling the processors to operate independently and simultaneously when no data transfer is occurring between them, and the apparatus includes data transfer circuitry connected between the processors for enabling the data to be transferred, a program instruction decoder associated with the second processor for normally decoding and executing instructions stored in the program instruction memory of the second processor when no data transfer is occurring, and routing circuitry for carrying the data transfer commands from the first processor to the program instruction decoder for decoding to provide signals to the data transfer circuitry to effect a transfer of data.

Processor interface circuitry for effecting data transfers between

A sample rate converter receives an input stream of samples representative of a time-varying signal and generates a corresponding output stream of samples which is also representative of the time-varying signal and in which each output stream sample appears at a desired time which may differ from the time when a sample appears in the input stream; filter circuitry receives the input stream and generates at least two intermediate samples which appear at different times, and interpolation circuitry combines selected intermediate samples to form a sample of the output stream at the desired time. In another aspect, an improvement is provided for a modem of the kind in which a line signal is sampled at times governed by an unstable clock to generate a first sample stream in which the samples appear with possibly changing sampling phases and a converter converts the first sample stream to a second stream of samples appearing at times that are possibly different from the times of appearance of the samples in the first sample stream; the improvement is means for providing to the converter signals representative of the changing phases of the samples in the first sample stream to cause the conversion to occur in a manner that reduces the contribution of the changing sampling phases to the times of appearance of the samples in the second sample stream.

Sample rate converter

In a modem that transmits signals to and receives signals from a remote device at a multiplicity of communication rates, the quality of the channel is monitored, a communication rate is selected based on the channel quality, the desire for an increased rate is indicated, and the increased rate is implemented by the modem when the remote device concurs.

Adaptive communication rate modem

A receiver for use in deciding which signal points were sent from a transmitter based on corresponding noise affected signals received over a channel, the transmitter including an encoder which encodes a stream of information symbols into the signal points, the noise affected signals carrying information about a particular sequence of possible states occupied in a succession of time intervals by a finite state process. The receiver includes feedback circuitry for generating a plurality of different modified versions of each received signal, and a decoder for deciding which signal points were sent, given the received signals, based on estimating the particular sequence of states, and using at least two different modified versions.

Coded modulation system with feedback

In one aspect the invention features a digital synthesizer having clock circuitry to provide a clock pulse train, synthesizer circuitry to provide a synthesized pulse train at a frequency such that multiple clock pulses occur between pairs of successive synthesized pulses, and phase control circuitry to cause an effective shift in the synthesized pulse train frequency by causing, between pairs of successive synthesized pulses, a number of phase shifts in the clock pulse train.

Frequency synthesizer and digital phase lock loop

Modem apparatus in which a modulated carrier signal represents digital bits, wherein the apparatus includes first digital processing circuitry having first programmable digital circuitry for arithmetic manipulation of digital values in accordance with selectable arithmetic program instructions to produce a correspondence between a sequence of signal values at a rate of 1/T signal values per second and a sequence of samples at a rate higher than 1/T samples per second representing the modulated carrier signal, where T represents the duration of a modulation period of the carrier signal, first bus circuitry connected to the first programmable digital circuitry for carrying the digital values and the arithmetic program instructions, and first memory circuitry connected to the first bus circuitry for storing the instructions, digital values, and signal values; second digital processing circuitry comprising second programmable digital circuitry for generating control signals corresponding to predetermined sequences of the arithmetic instructions, second bus circuitry connected to the second programmable circuitry for carrying the control signals, and second memory circuitry connected to the second bus circuitry for storing control signal program instructions; timing circuitry for timing the operation of the first and second processing circuitries, and means for providing a sequence of time-limited handshakes between the first and second processing circuitries, during which the control signals are transferred to the first processing circuitry to cause the first programmable digital circuitry to carry out the predetermined sequences of the arithmetic instructions.

Dual processor digital modem apparatus

Automatic gain control circuitry in a modem receiver, featuring a digitally controlled gain element for imposing on the received modulated carrier signal a gain corresponding to gain control signals g received from a microprocessor, an analog-to-digital converter to provide the microprocessor with digital samples of the received modulated carrier signal, and a gain control in the microprocessor for comparing an estimate of the average level of the samples with a desired level, and generating the control signals g based on the result of the comparison.

Modem circuitry

A data modulator for transmitting a first sequence of data symbols at a symbol rate of 1/T, the modulator being characterized as having a carrier frequency of f.sub.c Hz and the data symbols being denoted as x(kT), where x(kT) is a real or complex number and k is the time index of the kth symbol, featuring, in one aspect, modulated signal generating means for receiving the first sequence and generating, in response thereto and at the symbol rate, a second sequence of complex-valued signals y(kT), the signal y(kT) representing the complex number y(kT)=x(kT).multidot.exp (j2.pi.f.sub.c kT), where j=.sqroot.-1, and filter means for receiving the second sequence and generating, in response thereto, a third sequence of real-valued signals, at a rate higher than the symbol rate, the third sequence representing linear combinations of the real and imaginary parts of the second sequence of complex-valued signals y(kT).

Digital modem transmitter

Modem receiver apparatus having circuitry for receiving, demodulating, and decoding, at a first rate of 1/T bauds per second, a modulated double sideband carrier signal encoded to represent digital bits, wherein the received signal is converted to a stream of digital samples, the samples occurring at a sample rate higher than 1/T per second, and having timing recovery circuitry comprising phase-splitting filter circuitry connected to split the modulated double-sideband carrier signal sample stream into a pair of modulated carrier signal sample streams, the carrier frequencies associated with the pair of streams being equal but 90.degree. apart in phase, first circuitry connected to the output of the filter circuitry for generating a timing signal, and second circuitry connected in parallel with the first circuitry to the output of the filter circuitry for demodulating the output of said filter circuitry, the first circuitry comprising first circuitry for additionally filtering the output of said filter circuitry and providing, at a second rate at least as high as 2/T per second, successive values representative of the absolute value of the additionally filtered output, and second circuitry for generating the timing signal from the successive values provided by said first circuitry.

Time recovery circuitry in a modem receiver

In a high speed QAM data communications receiver of the type adapted to receive bursts of signals having a bandwidth B Hz and sent at a predetermined rate of 1/T signals per second over a channel, wherein the receiver includes an automatic adaptive equalizer having taps spaced equally apart, tap coefficient circuitry for repeatedly multiplying the output of each tap by a respective tap coefficient, and adjustment circuitry for adjusting the tap coefficients, and output circuitry responsive to the equalizer for providing output signals at times kT + .tau., k = 0, 1, . . . , where .tau. is a timing epoch, that improvement wherein the taps are spaced apart by T/n seconds, where n is greater than TB, and control circuitry is provided for early actuation of the adjustment circuitry to begin adjustment of the tap coefficients and hence training of the equalizer regardless of the initial value of the timing epoch, whereby the data capacity of the receiver is increased by reduction of the time required for set up of the receiver.

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Natick, MA, United States of America

Shahid U Qureshi