Sun Microsystems, Inc.

Shahid S Ansari

Deviprasad Malladi

Bidyut Kanti Sen

Steven R Boyle

Eric L Bogatin

Hanxi Chen

A method and system providing for electrical testing of an integrated semiconductor substrate having at least two signal processing layers. The substrate may be provided with a protective layer of plastic, silicon, silicon oxide, silicon nitride or the like. A selected region of one substrate layer to be tested electrically is exposed by etching or otherwise forming a controllably small aperture any overlying substrate layer(s) away to expos at least one selected circuit trace in the selected region and applying a selected electrical signal to the trace. Optionally, a second aperture, spaced apart from the first aperture, can be formed to expose a second selected circuit trace so that propagation of a signal in one or more substrate circuits can be tested. The aperture cross-sectional shapes may be linear or curvilinear polygons or other suitable shapes.

Efficient device debug system

A method for providing for electrical testing of an integrated semiconductor substrate having at least two signal processing layers. The substrate may be provided with a protective layer of plastic, silicon, silicon oxide, silicon nitride or the like. A selected region of one substrate layer to be tested electrically is exposed by etching or otherwise forming a controllably small aperture any overlying substrate layer(s) away to expose at least one selected circuit trace in the selected region and applying a selected electrical signal to the trace. Optionally, a second aperture, spaced apart from the first aperture, can be formed to expose a second selected circuit trace so that propagation of a signal in one or more substrate circuits can be tested. The aperture cross-sectional shapes may be linear or curvilinear polygons or other suitable shapes.

Efficient debug package design

A method and apparatus for testing an integrated circuit in a system level environment such that the integrated circuit to be tested is wired into a system or module when the testing occurs is disclosed. In one embodiment of a method aspect of the invention, a die in a packaged integrated circuit to be tested is exposed. A module that incorporates the exposed die is placed on a test platform. The test platform and a sensor probe are relatively positioned such that the sensor probe can directly monitor the exposed die during testing. The positioning may be accomplished by moving the test platform, the sensor probe or both. The system is then driven in a manner which exercises the exposed die. The sensor probe then directly monitor the die while the exposed die is being exercised. The die can be exposed in a variety of manners as for example by removing a package cover or by etching portions of the plastic packaging material. An integrated circuit tester suitable for implementing this process is also disclosed as well as a test board suitable for use when the integrated circuits being tested are cavity down packaged integrated circuits.

System level IC testing arrangement and method

Switching noise at integrated circuit V.sub.DD and V.sub.SS metal traces is reduced by minimizing lead inductance in on-chip bypass capacitors. For each on-chip bypass capacitor, a pair of V.sub.DD -carrying and V.sub.SS -carrying metal traces is formed, these traces having regions spaced-apart laterally a distance .DELTA.X corresponding to lateral separation of the bypass capacitor connecting pads. For each bypass capacitor, column-shaped openings, spaced-apart distance .DELTA.X, are formed through the passivation and inter-metal oxide layers, as needed. These openings expose and access regions of the pair of spaced-apart metal traces carrying V.sub.SS and V.sub.DD. These openings, which may be formed after the IC has been fabricated, preferably are formed using focussed ion beam technology ('FIB'). Alternatively, these openings may be formed using masking and etching steps. The column-shaped openings are then made into conductive columnar elements, preferably using FIB deposition of tungsten or platinum. Conductive element pads are formed atop the conductive columnar elements at the outer surface of the IC passivation layer. The bypass capacitors are then attached to the IC, and the capacitor connecting pads are electrically connected to the respective conductive element pads using conductive epoxy or other conductive bond material. This direct attachment of the on-chip bypass capacitors reduces effective capacitance lead inductance and improves attenuation of on-chip switching noise.

Method for direct attachment of an on-chip bypass capacitor in an

Switching noise at integrated circuit V.sub.DD and V.sub.SS metal traces is reduced by minimizing lead inductance in on-chip bypass capacitors. For each on-chip bypass capacitor, a pair of V.sub.DD -carrying and V.sub.SS -carrying metal traces is formed, these traces having regions spaced-apart laterally a distance .DELTA.X corresponding to lateral separation of the bypass capacitor connecting pads. For each bypass capacitor, column-shaped openings, spaced-apart distance .DELTA.X, are formed through the passivation and inter-metal oxide layers, as needed. These openings expose and access regions of the pair of spaced-apart metal traces carrying V.sub.SS and V.sub.DD. These openings, which may be formed after the IC has been fabricated, preferably are formed using focussed ion beam technology ('FIB'). Alternatively, these openings may be formed using masking and etching steps. The column-shaped openings are then made into conductive columnar elements, preferably using FIB deposition of tungsten or platinum. Conductive element pads are formed atop the conductive columnar elements at the outer surface of the IC passivation layer. The bypass capacitors are then attached to the IC, and the capacitor connecting pads are electrically connected to the respective conductive element pads using conductive epoxy or solder. This direct attachment of the on-chip bypass capacitors reduces effective capacitance lead inductance and improves attenuation of on-chip switching noise.

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Milpitas, CA, United States of America

Shahid S Ansari