International Business Machines Corporation

Infineon Technologies Ag

Other

Infineon Technologies North America Corp.

Globalfoundries Inc.

Shahid Ahmad Butt

Gerhard Kunkel

Allen H Gabor

Carl John Radens

Henning Haffner

Edward J Nowak

Brent A Anderson

Ramachandra Divakaruni

Jed Hickory Rankin

Robert C Wong

Timothy A Brunner

Donald J Samuels

Patrick Edward Lindo

John Ulrich Knickerbocker

Mukta G Farooq

Lars W Liebmann

Wayne Frederick Ellis

Harold Pilo

Katsuyuki Sakuma

Eric D Perfecto

Michael P Belyansky

Christopher P Ausschnitt

Qianwen Chen

Scott Marshall Mansfield

Alois Gutmann

Uwe Paul Schroeder

Daniel A Corliss

Munir D Naeem

Christopher Lee Tessler

Scott Josef Bukofsky

Shoaib Hasan Zaidi

Martin Burkhardt

Alan C Thomas

Zhijian Lu

Joseph P Kirk

Chung-Hsi J Wu

Pamela Castalino

Armin M Reith

Beate Frankowsky

Juergen Preuninger

Patrick Speno

Christian Summerer

A stack structure that includes: a device wafer, a handler wafer, and a bonding structure disposed between the device wafer and the handler wafer, wherein one or both of the device wafer and the handler wafer have a release layer that is configured to be substantially or completely vaporized by infrared ablation when exposed to an infrared laser energy. The device wafer includes at least two consecutive layers adjacent the bonding structure that together include a plurality of fill portions that substantially or completely disable entry of the infrared laser energy into a plurality of layers of the device wafer below the two consecutive layers adjacent the bonding structure.

Infrared debond damage mitigation by copper fill pattern

Disclosed are integrated circuit (IC) chip structures (e.g., radio frequency (RF) IC chip structures) and methods of forming the structures with an electrically insulative molding compound handler substrate. Each structure includes at least: an electrically insulative molding compound handler substrate; an insulator layer on the handler substrate; and one or more semiconductor devices (e.g., RF semiconductor devices) on the insulator layer. Each method includes at least: attaching a temporary carrier above back end of the line (BEOL) metal levels, which are over an interlayer dielectric layer covering one or more semiconductor devices; removing at least a portion of a semiconductor handler substrate, which is below the semiconductor device(s) and separated therefrom by an insulator layer; replacing the semiconductor handler substrate with a replacement handler substrate made of an electrically insulative molding compound; and removing the temporary carrier. The molding compound handler substrate provides backside isolation that prevents unwanted noise coupling.

Integrated circuit chip with molding compound handler substrate and method

Transistors are connected to ground outside of an SRAM array column. One transistor is connected from VSS to ground on the Q side of an SRAM cell. Another transistor is connected from VSS to ground on the Q' (Q complement) side of an SRAM cell. Each transistor is gated by is complementary bit line. The Q side transistor is gated by the BL&#x2032; (bit line complement, or 'BLC') line, and the Q&#x2032; side is gated by the BL line. The ground of the complement side is disconnected during a write operation to increase the performance of a state change during a write operation where a logical one is written to the Q node, thus improving write margin.

SRAM circuit with increased write margin

A method for forming a field effect transistor device includes patterning an arrangement of fin portions on a substrate, patterning a gate stack portion over portions of the fin portions and the substrate, growing an epitaxial material from the fin portions that electrically connects portions of adjacent fin structures, and removing a portion of the gate stack portion to expose a portion of the substrate.

FinFET device

Methods of forming adjacent polyconductor line ends and a mask therefor are disclosed. In one embodiment, the method includes forming a polyconductor layer over an isolation region; forming a mask over the polyconductor layer, the mask including shapes to create the polyconductor line ends and a correction element to ensure a designed proximity of the polyconductor line ends; and etching the polyconductor layer using the patterned photoresist mask to create the adjacent polyconductor line ends, wherein the correction element is removed during the etching.

Polyconductor line end formation and related mask

A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test devices distributed in different regions; and on a second wafer having the first arrangement of IC chips and the second arrangement of regions, adjusting a functional device parameter of identically designed field effect transistors within one or more regions of all IC chips of the second wafer based on a values of the test device parameter measured on test devices in regions of the IC chip of the first wafer by a non-uniform adjustment of physical or metallurgical polysilicon gate widths of the identically designed field effect transistors from region to region within each IC chip.

Methods for reducing within chip device parameter variations

A method for optimizing imaging and process parameter settings in a lithographic pattern imaging and processing system is disclosed. The method includes correlating the dimensions of a first set of at least one control pattern printed in a lithographic resist layer, measured at three or more locations on or within the pattern which correspond to differing dose, defocus and blur sensitivity. The method then includes measuring the dimensions on subsequent sets of control patterns, printed in a lithographic resist layer, at three or more locations on or within each pattern, of which a minimum of three locations match those measured in the first set, and determining the effective dose, defocus and blur values associated with forming the subsequent sets of control patterns by comparing the dimensions at the matching locations with the correlated dependencies. A method for determining blur, focus and exposure dose error in lithographic imaging is also disclosed.

Focus blur measurement and control method

An active area pattern is formed atop a deep trench pattern with a single exposure using an alternative phase-shift mask. To prevent adjacent spaces of opposite phase from intersecting one another at the ends of substantially opaque features of the active area pattern, one or more connectors are used to connect the ends of the substantially opaque patterns. Trench regions of the deep trench pattern are arranged such that the conduction path of the connectors are interrupted and prevent the lines from shorting to one another. Alternatively, a bit line pattern or a word line pattern having a lines and spaces array and a support region are printed with a single exposure using an alternating phase-shift mask. At one end of the array region, lines having a respective phase shift extend into the support region, and lines of the opposite phase shift are terminated. At the opposite end of the array, the lines that have the opposite phase shift extend into the support region, and the lines of having the respective phase shift are terminated.

Single exposure of mask levels having a lines and spaces array using alternating phase-shift mask

Method for reducing within chip device parameter variations

Non-uniformity and image shortening are substantially reduced in an image printed on a substrate using a photolithographic mask in which the mask pattern includes at least one lines and spaces array adjacent to at least one clear region. At least one line feature is incorporated within the clear region of the mask pattern and is disposed in proximity to the lines and spaces array. The line feature has a line width that is smaller than a minimum resolution of the optical projection system. The image is printed by illuminating the photolithographic mask and projecting light transmitted through the photolithographic mask onto the substrate using the optical projection system.

Critical dimension control of printed features using non-printing fill patterns

The relative surface area sizes of portions having distinct phase-shift and transmission of light of a pattern on a phase-shift mask substantially obey the condition that the product of surface area and transmission of the electrical field strength is the same for all of the portions. Then, frequency doubling occurs due to vanishing zero order diffraction orders and in the case of high-transition attenuated phase-shift masks a large first order diffraction amplitude reveals an even an improved as compared with conventional phase-shift masks. Two-dimensional matrix-like structures particularly on attenuated or halftone phase-shift masks can be arranged to image high-density patterns on a semiconductor wafer. The duty cycles of pattern matrices can be chosen being different from one in two orthogonal directions nevertheless leading to frequency doubling.

Phase-shift mask

A mask is configured for projecting a structure pattern onto a semiconductor substrate in an exposure unit. The exposure unit has a minimum resolution limit for projecting the structure pattern onto the semiconductor substrate. The mask has a substrate, at least one raised first structure element on the substrate which has a lateral extent which is at least the minimum lateral extent that can be attained by the exposure unit, a configuration second raised structure elements which are arranged in an area surrounding the at least one first structure element on the substrate in the form of a matrix with a row spacing and a column spacing, whose shape and size are essentially identical to one another, and which have a respective lateral extent that is less than the minimum resolution limit of the exposure unit.

Mask for projecting a structure pattern onto a semiconductor substrate

A method and system for detecting the quality of an alternating phase shift mask having a number of 180-degree phase shift areas alternating with a number of 0-degree phase shift areas is disclosed. In operation, a light source which provides wavelength-adjustable incident lights illuminates the incident lights on the alternating phase shift mask. The light outputs from boundaries between the 0-degree phase shift areas and the 180-degree phase shift areas of the alternating phase shift mask are detected. Relation curves of the wavelength of the incident light and a light intensity of the boundaries are then calculated. Phase errors of the alternating phase shift mask can thus be measured from the relation curves.

System and method for quantifying errors in an alternating phase shift mask

Growing community of inventors

Ossining, NY, United States of America

Shahid Ahmad Butt