Adaptec, Inc.

Shahe H Krakirian

A method and apparatus for generating multiple frequency clock signals using a single input clock signal are provided. Each clock signal generated has a cycle time that is an integer multiple of the input clock cycle time. The fastest clock signal, i.e., the clock signal with the highest frequency generated has the same cycle time as the input clock. The rising edges of all the clock signals generated are synchronized and each clock signal generated has an approximate duty cycle of 50%. This is achieved by first applying the input clock signal to an input terminal of a plurality of registers and of a frequency control module of the signal generator, presenting control signals to input terminals of the registers and of the frequency control module, and generating a plurality of output clock signals in the frequency control module, dependent on the input clock signal and on the control signals.

Multiple frequency clock generation and synchronization

A method and apparatus for performing XOR operations on a hard disk drive are provided, which optimize the buffer bandwidth with minimal logic added to the hard disk controller integrated circuit. This is achieved by first storing data from a first source in the buffer memory in an interleaved fashion (i.e. at memory locations having addresses k, k+2 . . . ,k+2n-2) and then sequentially reading each bit set from the buffer memory, XORing it with a corresponding bit set read from a second source and writing the result at the next consecutive location in the buffer memory (i.e. at memory locations having addresses k+1, k+3 . . . k+2n-1). The method can be implemented on existing hard disk controllers with minimal modifications to the hardware. In addition, an embodiment of the invention allows for decoupling of the XOR operation from disk and host transfers, allowing each of those transfers to occur at their maximum rate and using the remaining buffer bandwidth for the XOR operation.

Interleaved burst XOR using a single memory pointer

A hard disk controller integrated circuit of a SCSI target device comprises a sequencer which causes a SCSI bus to transition from a command bus phase to a data transfer bus phase during execution of an autoread or an autowrite SCSI command without waiting for a communication from a microprocessor of the SCSI target device. In some embodiments, the command is determined to be either an autotransfer command or a non-autotransfer command. If the command is a non-autotransfer command, then the sequencer does not proceed directly to the data transfer phase but rather requires microprocessor intervention before proceeding to the data transfer phase. In some embodiments, an autotransfer command (such as an autoread or an autowrite command) is carried out by the disk drive controller integrated circuit with only two interrupts being generated to the microprocessor: one after receiving the autotransfer command from the initiator; and one after data transfer of the autotransfer command is complete. The hard disk controller integrated circuit automatically sends the status byte and command complete message if there is no queue tag collision as indicated by a cleared tag not okay flag.

System for supplying initiator identification information to SCSI bus in

A hard disk controller integrated circuit of a SCSI target device comprises a sequencer which causes a SCSI bus to transition from a command bus phase to a data transfer bus phase during execution of an autoread or an autowrite SCSI command without waiting for a communication from a microprocessor of the SCSI target device. In some embodiments, the command is determined to be either an autotransfer command or a non-autotransfer command. If the command is a non-autotransfer command, then the sequencer does not proceed directly to the data transfer phase but rather requires microprocessor intervention before proceeding to the data transfer phase. In some embodiments, an autotransfer command (such as an autoread or an autowrite command) is carried out by the disk drive controller integrated circuit with only two interrupts being generated to the microprocessor: one after receiving the autotransfer command from the initiator; and one after data transfer of the autotransfer command is complete. The hard disk controller integrated circuit automatically sends the status byte and command complete message if there is no potential queue tag collision as indicated by a cleared tag not okay flag.

System for storing initiator, queue tag and logical block information,

A hard disk controller integrated circuit of a SCSI target-device comprises a sequencer which causes a SCSI bus to transition from a command bus phase to a data transfer bus phase during execution of an autoread or an autowrite SCSI command without waiting for a communication from a microprocessor of the SCSI target device. In some embodiments, the command is determined to be either an autotransfer command or a non-autotransfer command. If the command is a non-autotransfer command, then the sequencer does not proceed directly to the data transfer phase but rather requires microprocessor intervention before proceeding to the data transfer phase. In some embodiments, an autotransfer command (such as an autoread or an autowrite command) is carried out by the disk drive controller integrated circuit with only two interrupts being generated to the microprocessor: one after receiving the autotransfer command from the initiator; and one after data transfer of the autotransfer command is complete. The hard disk controller integrated circuit automatically sends the status byte and command complete message if there is no potential queue tag collision as indicated by a cleared tag not okay flag.

Method for receiving a first SCSI command, subsequent receiving second

System for generating second interrupt signal for data transfer

System for starting and completing a data transfer for a subsequently

Method of flagging the completion of a second command before the

A hard disk controller integrated circuit of a SCSI target device comprises a dedicated command descriptor block 'CDB' parsing state machine. The dedicated CDB parsing state machine parses incoming six-byte, ten-byte and twelve-byte SCSI command descriptor blocks and writes information from corresponding fields in the six-byte, ten-byte and twelve-byte SCSI command descriptor blocks into predetermined memory locations. In some embodiments, there are sixteen such predetermined memory locations which together comprise a 16.times.8 register file. A microprocessor coupled to the hard disk controller integrated circuit is therefore relieved of the burden of parsing incoming SCSI command descriptor blocks.

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Milpitas, CA, United States of America

Shahe H Krakirian