Technion Research & Development Foundation Ltd

Shahar Kvatinsky

Avinoam Kolodny

Loai Danial

Ran Ginosar

Guy Satat

Daniel Soudry

Eilam Yalon

Nicolas Wainstein

Avishay Drori

Dmitry Belousov

Slavik Liman

Elad Amrani

Nimrod Wald

Eby G Friedman

Dotan Di Castro

Leonid Yavits

Amir Morad

Leonid Azriel

Ravi Patel

Uri Weiser

Asaf Gal

Yifat Hanein

Barak Hoffer

Ben Perach

Misbah Ramadan

Tzofnat Greenberg

An indirectly heated phase change switch (IPCS) for radio frequency (RF) switching, comprises two RF ports and an RF path therebetween, a phase change material (PCM) located between the RF ports, an embedded heater separated from the PCM by a dielectric layer, the embedded heater configured to provide thermal actuation of the PCM to bring about phase changes between a crystalline state and an amorphous state to provide Ohmic switching, and a bias voltage on the IPCS across said RF path. The bias is provided during heating to improve the crystallization time.

Apparatus and method for ultra-fast crystallization in phase-change RF switches

An electronic memory block comprises phase change memory cells for memory storage and further phase change memory cells forming logic gates, to provide in-memory data processing.

Logic gates and stateful logic using phase change memory

A method, comprising: providing an electrical energy source having a specified amount of electrical energy; connecting an array comprising n magnetic tunnel junctions (MTJ) in parallel to said electrical energy source, wherein each of said MTJs is at a high resistance initial state; discharging said specified energy amount through said MTJs, thereby causing a random subset of said MTJs to switch to a lower resistance state; determining a post-discharging resistance state of each of the MTJs; and assigning a logical state to each of said MTJs corresponding to said resistance state of said MTJ.

Asynchronous true random number generator using STT-MTJ

A stochastic synapse for use in a neural network, comprising: first and second magnetic tunnel junction (MTJ) devices, each MTJ device having a fixed layer port and a free layer port; a first and second control circuit, each connected respectively to the free layer port of the first and second MTJ devices, wherein the fixed layer ports of the first and second MTJ devices are connected to each other; wherein the first and second control circuits are configured to perform a gated XNOR operation between synapse and activation values; and wherein an output of the gated XNOR is represented by the output current through both of the first and second MTJ devices.

MTJ-based hardware synapse implementation for binary and ternary deep neural networks

An analog to digital converter comprises an input for receiving an analog input signal; a plurality of outputs for outputting parallel bits of a digital signal that represents said analog input signal; and a neural network layer providing connections between each of said outputs respectively, each connection having an adjustable weighting. The synapses of the neural networks may be memristors and training may use online gradient descent.

Analog to digital converter using memristors in a neural network

A digital to analog converter is constructed using a neural network layer. The converter has inputs for receiving parallel bits of a digital input signal and an output for outputting an analog signal which is based on the digital input. Connecting the input and the output is a neural network layer which is configured to convert the parallel bits into an output analog signal that is representative of the digital input signal. The neural network may be hardwired and the synapses may rely on memristors as programmable elements.

Reconfigurable DAC implemented by memristor based neural network

A pipelined ADC system comprising: a first ADC stage comprising a trainable neural network layer and configured to receive an analog input signal, and convert it into a first n-bit digital output representing said analog input signal; a DAC circuit comprising a trainable neural network layer and configured to receive said first n-bit digital output, and convert it into an analog output signal representing said first n-bit digital output; and a second ADC stage comprising a trainable neural network layer and configured to receive a residue analog input signal of said analog input signal, and convert it into a second n-bit digital output representing said residue analog input signal; wherein said first and second n-bit digital outputs are combined to generate a combined digital output representing said analog input signal.

Analog-to-digital converter using a pipelined memristive neural network

A hybrid computer that comprises a sequential processor, a single instruction massively parallel (SIMD) processor, and shared memory module that is shared between the sequential processor and the SIMD processor.

Hybrid processor

Logic gates are made from first and second resistive elements connected together to form a voltage divider. One or both of the resistive elements is a unipolar memristor. OR and NOT gates may be constructed to make a digital logic system.

Logic design with unipolar memristors

Apparatus and method for hashing a message, comprises using an array of individually selectable memristor cells. The memristor cells are subject to write disturb that affects cells neighboring a selected cell so that a write operation into one cell has a knock-on effect on the neighbors. The array is initiated into a known stable state so that these changes to neighboring cells are predictable according to proximity to the currently selected cell. An inserter sequentially mixes bits with the hash so far to insert bits into successively selected cells of the memristor array and forms a succession of memristor array states including the knock on effects on the neighboring cells. A final resulting memristor array state following input of the bits forms the hash of the message.

Memresistive security hash function

A method and a device that includes a set of multiple pipeline stages, wherein the set of multiple pipeline stages is arranged to execute a first thread of instructions; multiple memristor based registers that are arranged to store a state of another thread of instructions that differs from the first thread of instructions; and a control circuit that is arranged to control a thread switch between the first thread of instructions and the other thread of instructions by controlling a storage of a state of the first thread of instructions at the multiple memristor based registers and by controlling a provision of the state of the other thread of instructions by the set of multiple pipeline stages; wherein the set of multiple pipeline stages is arranged to execute the other thread of instructions upon a reception of the state of the other thread of instructions.

Memristor based multithreading

Memory circuitry comprises memory cells having two terminals and a feedback path connected between the two terminals. The feedback path is used to adaptively amplify identical programming pulses that serve to change memory states of the memory cell, and the amplification is based on a current resistive level of the memory cell, which may for example be a multi-level memory cell.

Programming for electronic memories

According to an embodiment of the invention there is provided a device and method. The device may include a pure memristive logic gate, wherein the pure memristive logic gate consists essentially of at least one input memristive device and an output memristive device that is coupled to and differs from the at least one memristive device; wherein the pure memristive device is controlled by a single control voltage.

Pure memristive logic gate

A device, comprising: an array of cells, wherein the cells are arranged in columns and rows; wherein each cell comprises a memristive device; an interfacing circuit that is coupled to each cell of the array of cells; wherein the interfacing circuit is arranged to: receive or generate first variables and second variables; generate memristive device input signals that once provided to memristive devices of the array will cause a change in a state variable of each of the memristive devices of the cells of the array, wherein the change in the state variable of each of the memristive devices of the cells of array reflects a product of one of the first variables and one of the second variables; provide the memristive device input signals to memristive devices of the array; and receive output signals that are a function of at least products of the first variables and the second variables.

Growing community of inventors

Ramat Gan, Israel

Shahar Kvatinsky