Taiwan Semiconductor Manufacturing Comp. Ltd.

Shahaji B More

Shih-Chieh Chang

Cheng-Han Lee

Chandrashekhar Prakash Savant

Chun Hsiung Tsai

Zheng-Yang Pan

Kuo-Feng Yu

Huai-Tei Yang

Cheng-Yi Peng

Chun-Chieh Wang

Chih-Yu Ma

Shu Kuan

Yu-Ming Lin

Chia-Ming Tsai

Chun-Hsiung Tsai

Tien-Wei Yu

Clement Hsingjen Wann

Jian-Hao Chen

Cheng-Wei Chang

Chien Lin

Yi-Min Huang

Ming-Hsi Yeh

Yen-Ming Chen

Chih-Hsin Ko

Wei-Yang Lee

Da-Wen Lin

Yueh-Ching Pai

Ya-Yun Cheng

Yi-Ying Liu

Yin-Pin Wang

Chun Chieh Wang

Ziwei Fang

Tsung-Lin Lee

Chee-Wee Liu

Kun-Yu Lee

Chung-En Tsai

Shih-Ya Lin

Chung-Hsien Yeh

Pei-Shan Lee

Jia-Ying Ma

Sung-Li Wang

Shuen-Shin Liang

Wei-Jen Lo

Chien-Feng Lin

Ching-Lun Lai

Chi-Yu Chou

Wen Han Hung

Yi Chen Ho

Che-Chih Hsu

Chinyu Su

Chi-Hsun Lin

Yu-Chuan Chen

Po-Han Tseng

Clement Hsinghen Wann

Sheng-Syun Wong

Chih Yung Hung

Chieh Cheng

A semiconductor device and a method of forming the same are provided. A method includes forming a sacrificial gate over an active region of a substrate. The sacrificial gate is removed to form an opening. A gate dielectric layer is formed on sidewalls and a bottom of the opening. A first work function layer is formed over the gate dielectric layer in the opening. A first protective layer is formed over the first work function layer in the opening. A first etch process is performed to widen an upper portion of the opening. The opening is filled with a conductive material.

Gate structure and method of forming same

Some implementations described herein provide techniques and apparatuses for forming insulator layers in or on a semiconductor substrate prior to forming epitaxial layers within source/drain regions of a fin field-effect transistor. The epitaxial layers may be formed over the insulator layers to reduce electron tunneling between the source/drain regions of the fin field-effect transistor. In this way, a likelihood of leakage into the semiconductor substrate and/or between the source/drain regions of the fin field-effect transistor is reduced.

Semiconductor device and manufacturing methods thereof

A semiconductor device includes a gate structure disposed over a channel region and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, one or more work function adjustment material layers over the gate dielectric layer, and a metal gate electrode layer over the one or more work function adjustment material layers. The one or more work function adjustment layers includes an aluminum containing layer, and a diffusion barrier layer is disposed at at least one of a bottom portion and a top portion of the aluminum containing layer. The diffusion barrier layer is one or more of a Ti-rich layer, a Ti-doped layer, a Ta-rich layer, a Ta-doped layer and a Si-doped layer.

Method of manufacturing semiconductor devices and semiconductor devices

A method includes forming an N well and a P well in a substrate; depositing a first layer having silicon over the N well and the P well; depositing a first dielectric layer over the first layer; forming a resist pattern over the first dielectric layer, the resist pattern providing an opening directly above the N well; etching the first dielectric layer and the first layer through the opening, leaving a first portion of the first layer over the N well; removing the resist pattern; and epitaxially growing a second layer having silicon germanium (SiGe) over the first portion of the first layer. The epitaxially growing the second layer includes steps of (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a SiGe layer over the silicon seed layer, wherein the steps (a), (b), and (c) are performed under about a same temperature.

Method of forming fully strained channels

Some implementations described herein provide a nanostructure transistor including inner spacers between a gate structure and a source/drain region. The inner spacers, formed in cavities at end regions of sacrificial nanosheets during fabrication of the nanostructure transistor, include concave-regions that face the source/drain region. Formation techniques include forming the sacrificial nanosheets and inner spacers to include certain geometric and/or dimensional properties, such that a likelihood of defects and/or voids within the inner spacers and/or the gate structure are reduced.

Semiconductor device and methods of formation

In some implementations, a buffer layer is formed under a source/drain region of a device. A shape of the buffer layer may include a curved top surface having a height that extends to increase coverage of nanosheets of a fin structure of the device. The shape also includes regions having widths that extend towards shallow trench isolation regions of the device. The shape reduces a likelihood of dopants diffusing from the source/drain region into a mesa region of the fin structure. As a result, a performance of the device may be increased by decreasing short channel effects, decreasing an off-current of the device, and decreasing leakage within the device, among other examples.

Semiconductor device and methods of manufacturing

In an embodiment, a device includes: a first insulating fin; a second insulating fin; a nanostructure between the first insulating fin and the second insulating fin; and a gate structure wrapping around the nanostructure, a top surface of the gate structure disposed above a top surface of the first insulating fin, the top surface of the gate structure disposed below a top surface of the second insulating fin.

Transistor gate contacts and methods of forming the same

In a method of manufacturing a semiconductor device, first and second fin structures are formed over a substrate, an isolation insulating layer is formed over the substrate, a gate structure is formed over channel regions of the first and second fin structures, source/drain regions of the first and second fin structure are recessed, and an epitaxial source/drain structure is formed over the recessed first and second fin structures. The epitaxial source/drain structure is a merged structure having a merger point, and a height of a bottom of the merger point from an upper surface of the isolation insulating layer is 50% or more of a height of the channel regions of the first and second fin structures from the upper surface of the isolation insulating layer.

Method of manufacturing a semiconductor device and a semiconductor device

A device includes a first gate region having a first gate length; a first spacer on a sidewall of the first gate region; a semiconductor layer over the first gate region; a second gate region over the semiconductor layer, wherein the second gate region has a second gate length equal to the first gate length; and a second spacer on a sidewall of second gate region, wherein the second spacer is wider than the first spacer.

Methods of forming gate structures with uniform gate length

In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first work function adjustment material layer is formed over the gate dielectric layer, an adhesion enhancement layer is formed on the first work function adjustment material layer, a mask layer including an antireflective organic material layer is formed on the adhesion enhancement layer, and the adhesion enhancement layer and the first work function adjustment material layer are patterned by using the mask layer as an etching mask. The adhesion enhancement layer has a higher adhesion strength to the antireflective organic material layer than the first work function adjustment material layer.

A gate structure of a field effect transistor includes a first gate dielectric layer, a second gate dielectric layer, and one or more conductive layers disposed over the first gate dielectric layer and the second gate dielectric layer. The first gate dielectric layer is separated from the second gate dielectric layer by a gap filled with a diffusion blocking layer.

In a method of manufacturing a semiconductor device, an upper fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed over a lower fin structure, a sacrificial gate structure is formed over the upper fin structure, a source/drain region of the upper fin structure, which is not covered by the sacrificial gate structure, is etched thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, an inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers, and a source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. In etching the source/drain region, a part of the lower fin structure is also etched to form a recess, in which a (111) surface is exposed.

Some implementations described herein provide a nanostructure transistor and methods of formation. The nanostructure transistor includes concave-shaped regions at ends of a plurality of channel layers. The nanostructure transistor further includes convex-shaped portions of an epitaxial material, included as part of a source/drain region of the nanostructure transistor, that extend into the concave-shaped regions. Masking, etching, and cleaning operations, performed after deposition of a buffer layer, may form the concave-shaped regions.

An embodiment device includes: an isolation region on a substrate; a first fin extending above a top surface of the isolation region; a gate structure on the first fin; and an epitaxial source/drain region adjacent the gate structure, the epitaxial source/drain region having a first main portion and a first projecting portion, the first main portion disposed in the first fin, the first projecting portion disposed on a first sidewall of the first fin and beneath the top surface of the isolation region.

Semiconductor device and method

In a method of manufacturing a semiconductor device, a fin structure is formed. The fin structure includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure, and a hard mask layer over the stacked layer. An isolation insulating layer is formed so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed, and a second dielectric layer made of a different material than the first dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer, thereby forming a wall fin structure.

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Hsinchu, Taiwan

Shahaji B More