Taiwan Semiconductor Manufacturing Comp. Ltd.

Shahaji B More

Shih-Chieh Chang

Cheng-Han Lee

Chandrashekhar Prakash Savant

Chun Hsiung Tsai

Zheng-Yang Pan

Kuo-Feng Yu

Huai-Tei Yang

Cheng-Yi Peng

Chun-Chieh Wang

Chih-Yu Ma

Yu-Ming Lin

Shu Kuan

Clement Hsingjen Wann

Chun-Hsiung Tsai

Chia-Ming Tsai

Tien-Wei Yu

Yi-Min Huang

Jian-Hao Chen

Cheng-Wei Chang

Chien Lin

Ming-Hsi Yeh

Chih-Hsin Ko

Yen-Ming Chen

Wei-Yang Lee

Da-Wen Lin

Yueh-Ching Pai

Ya-Yun Cheng

Yi-Ying Liu

Yin-Pin Wang

Chun Chieh Wang

Ziwei Fang

Tsung-Lin Lee

Chee-Wee Liu

Kun-Yu Lee

Chung-En Tsai

Shih-Ya Lin

Chung-Hsien Yeh

Pei-Shan Lee

Jia-Ying Ma

Sung-Li Wang

Shuen-Shin Liang

Wei-Jen Lo

Chien-Feng Lin

Ching-Lun Lai

Chi-Yu Chou

Wen Han Hung

Yi Chen Ho

Che-Chih Hsu

Chinyu Su

Chi-Hsun Lin

Yu-Chuan Chen

Po-Han Tseng

Sheng-Syun Wong

Chih Yung Hung

Chieh Cheng

Some implementations described herein include a semiconductor device including a gate-all-around transistor. The gate-all-around transistor includes a source/drain region having a core epitaxial layer and a capping epitaxial layer. The core epitaxial layer is formed within the source/drain region using a deposition recipe having a temperature that is lesser relative to temperatures of other deposition recipes used to form other epitaxial layers, including the capping layer, within the source/drain region. The deposition recipe further includes a pressure that is greater relative to pressures of the other deposition recipes used to form the other epitaxial layers within the source/drain region. The temperature and pressure of the deposition recipe used to form the core epitaxial layer promote a uniform growth of the core epitaxial layer within the source/drain region. In this way, a likelihood of voids and/or defects is reduced to increase a yield of a semiconductor device including the core epitaxial layer.

Semiconductor device and methods of formation

In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.

Method of manufacturing a semiconductor device

In an embodiment, a device includes: a gate structure over a substrate; a gate spacer adjacent the gate structure; a source/drain region adjacent the gate spacer; a first inter-layer dielectric (ILD) on the source/drain region, the first ILD having a first concentration of an impurity; and a second ILD on the first ILD, the second ILD having a second concentration of the impurity, the second concentration being less than the first concentration, top surfaces of the second ILD, the gate spacer, and the gate structure being coplanar; and a source/drain contact extending through the second ILD and the first ILD, the source/drain contact coupled to the source/drain region.

Inter-layer dielectrics and etch stop layers for transistor source/drain regions

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) having a portion within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via.

Interconnect layout for semiconductor device

A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.

Semiconductor device and methods of forming same

A method includes forming a first fin and a second fin over a substrate, depositing an isolation material surrounding the first and second fins, forming a gate structure along sidewalls and over upper surfaces of the first and second fins, recessing the first and second fins outside of the gate structure to form a first recess in the first fin and a second recess in the second fin, epitaxially growing a first source/drain material protruding from the first and second recesses, and epitaxially growing a second source/drain material on the first source/drain material, wherein the second source/drain material grows at a slower rate on outermost surfaces of opposite ends of the first source/drain material than on surfaces of the first source/drain material between the opposite ends of the first source/drain material, and wherein the second source/drain material has a higher doping concentration than the first source/drain material.

FinFET structures and methods of forming the same

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, and a source/drain (S/D) region adjacent to the gate structure. The S/D region can include first and second side surfaces separated from each other. The S/D region can further include top and bottom surfaces between the first and second side surfaces. A first separation between the top and bottom surfaces can be greater than a second separation between the first and second side surfaces.

Source/drain structure for semiconductor fin field effect transistor (finFET) device having graded germanium

Disclosed are methods for manufacturing semiconductor devices that include the operations of forming a first interconnect segment over a semiconductor substrate, forming a cap layer of a first metal over a top surface of the first interconnect segment, and modifying an exposed surface of the cap layer to form an organometallic film by adding ammonia to the top surface of the cap layer, reacting a portion of the ammonia with residual methyl radicals present on the top surface of the cap layer, and removing hydrogen from both the ammonia and the methyl radicals to form an organometallic film on the cap layer.

Semiconductor device with low-galvanic corrosion structures, and method of making same

A semiconductor device and a method of forming the same are provided. A method includes forming a sacrificial gate over an active region of a substrate. The sacrificial gate is removed to form an opening. A gate dielectric layer is formed on sidewalls and a bottom of the opening. A first work function layer is formed over the gate dielectric layer in the opening. A first protective layer is formed over the first work function layer in the opening. A first etch process is performed to widen an upper portion of the opening. The opening is filled with a conductive material.

Gate structure and method of forming same

Some implementations described herein provide techniques and apparatuses for forming insulator layers in or on a semiconductor substrate prior to forming epitaxial layers within source/drain regions of a fin field-effect transistor. The epitaxial layers may be formed over the insulator layers to reduce electron tunneling between the source/drain regions of the fin field-effect transistor. In this way, a likelihood of leakage into the semiconductor substrate and/or between the source/drain regions of the fin field-effect transistor is reduced.

Semiconductor device and manufacturing methods thereof

A semiconductor device includes a gate structure disposed over a channel region and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, one or more work function adjustment material layers over the gate dielectric layer, and a metal gate electrode layer over the one or more work function adjustment material layers. The one or more work function adjustment layers includes an aluminum containing layer, and a diffusion barrier layer is disposed at at least one of a bottom portion and a top portion of the aluminum containing layer. The diffusion barrier layer is one or more of a Ti-rich layer, a Ti-doped layer, a Ta-rich layer, a Ta-doped layer and a Si-doped layer.

Method of manufacturing semiconductor devices and semiconductor devices

A method includes forming an N well and a P well in a substrate; depositing a first layer having silicon over the N well and the P well; depositing a first dielectric layer over the first layer; forming a resist pattern over the first dielectric layer, the resist pattern providing an opening directly above the N well; etching the first dielectric layer and the first layer through the opening, leaving a first portion of the first layer over the N well; removing the resist pattern; and epitaxially growing a second layer having silicon germanium (SiGe) over the first portion of the first layer. The epitaxially growing the second layer includes steps of (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a SiGe layer over the silicon seed layer, wherein the steps (a), (b), and (c) are performed under about a same temperature.

Method of forming fully strained channels

Some implementations described herein provide a nanostructure transistor including inner spacers between a gate structure and a source/drain region. The inner spacers, formed in cavities at end regions of sacrificial nanosheets during fabrication of the nanostructure transistor, include concave-regions that face the source/drain region. Formation techniques include forming the sacrificial nanosheets and inner spacers to include certain geometric and/or dimensional properties, such that a likelihood of defects and/or voids within the inner spacers and/or the gate structure are reduced.

In some implementations, a buffer layer is formed under a source/drain region of a device. A shape of the buffer layer may include a curved top surface having a height that extends to increase coverage of nanosheets of a fin structure of the device. The shape also includes regions having widths that extend towards shallow trench isolation regions of the device. The shape reduces a likelihood of dopants diffusing from the source/drain region into a mesa region of the fin structure. As a result, a performance of the device may be increased by decreasing short channel effects, decreasing an off-current of the device, and decreasing leakage within the device, among other examples.

Semiconductor device and methods of manufacturing

In an embodiment, a device includes: a first insulating fin; a second insulating fin; a nanostructure between the first insulating fin and the second insulating fin; and a gate structure wrapping around the nanostructure, a top surface of the gate structure disposed above a top surface of the first insulating fin, the top surface of the gate structure disposed below a top surface of the second insulating fin.

Transistor gate contacts and methods of forming the same

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Hsinchu, Taiwan

Shahaji B More