Apple Inc.

Infinera Corporation

Shah M Sharif

Brian S Leibowitz

Jafar Savoj

Fu-Tai An

Ryan D Bartling

A cross-domain power control circuit is disclosed. The circuit includes a first circuit branch having a first transistor coupled to a first supply voltage node and a second circuit branch having a second transistor coupled to the first supply voltage node. A third circuit branch is coupled between a second supply voltage node and a third supply voltage node. A second supply voltage conveyed on the second supply voltage node is less than a first supply voltage conveyed on the first supply voltage node. A fourth circuit branch is coupled between the first and third supply voltage nodes. In a first mode of operation, control circuitry causes the second supply voltage to be conveyed to the third supply voltage node. In a second mode of operation, the control circuitry causes the first supply voltage to be conveyed to the third supply voltage node.

Cross-domain power control circuit

A serial data receiver circuit included in a computer system may include a front-end circuit, a sample circuit that includes multiple analog-to-digital converter circuits, and a recovery circuit. The front-end circuit may generate an equalized signal using multiple signals that encode a serial data stream of multiple data symbols. Based on a baud rate of the serial data stream, a determined number of the multiple analog-to-digital converter circuits sample, using a recovered clock signal, the equalized signal at the respective times to generate corresponding samples. The recovery circuit generates, using the samples, the recovered clock signal and recovered data symbols.

Latency reduction in analog-to-digital converter-based receiver circuits

Methods and apparatuses are described herein for metastability error detection and correction in analog-to-digital converters (ADCs). For example, an ADC may comprise a comparator, a register circuit, a first circuit, and a second circuit. The comparator may generate a comparator output signal in response to a sampling clock signal. The register circuit, operatively coupled to the comparator, may process the comparator output signal. The first circuit, operatively coupled to the comparator and the register circuit may generate a plurality of first output bits that include a bit indicating a metastability error on a condition that the metastability error occurred during the bit conversion. The second circuit, operatively coupled to the first circuit, may generate a plurality of second output bits indicating a location of the metastability error. The plurality of second output bits may be sampled using first and second groups in response to the sampling clock signal.

Metastability error correction methods and circuits for asynchronous successive approximation analog to digital converter (SAR ADC)

A method and apparatus are disclosed for asynchronous clock generation in analog-to-digital converters (ADCs). For example, an ADC may comprise a comparator, a first logic gate, a second logic gate, a first memory element, a second memory element, and a digital-to-analog converter (DAC). The comparator may initiate an evaluation or precharge operation of comparator inputs. The first logic gate may generate, based on comparator outputs, a first output signal indicating validity of first logic gate output. The second logic gate may generate a second output signal indicating timing reference of bit conversion. The first memory element may generate a third output signal indicating a current state of a bit. The second memory element may generate a plurality of next state bits based on the second output signal and the comparator outputs. The second logic gate may generate the second output signal based on the first and third output signals.

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San Jose, CA, United States of America

Shah M Sharif