Texas Instruments Corporation

Shagun Dusad

Visvesvaraya Appala Pentakota

Srinivas Kumar Reddy Naru

Eeshan Miglani

Neeraj Shrivastava

Chirag Chandrahas Shetty

Sandeep Kesrimal Oswal

Rishi Soundararajan

Jagannathan Venkataraman

Viswanathan Nagarajan

Narasimhan Rajagopal

Sai Aditya Krishnaswamy Nurani

Ani Xavier

Prasanth K

Arun Kumar Mohan

Vajeed Nimran

Sai Aditya Nurani

Nagarajan Viswanathan

Rajendrakumar Joish

William J Bright

Raja Reddy Patukuri

Karthikeyan Gunasekaran

Mark B Weaver

Roswald Francis

Naveen Mahadev

Nithin Gopinath

Jiankun Hu

Joseph Palackal Mathew

Shabbir Amjhera Wala

Santhosh Kumar Gowdhaman

Anand Jerry George

Visvesvaraya Pentakota Appala

Vysakh Karthikeyan

Raja Sekhar

Jaiganesh Balakrishnan

Sarma Sundareswara Gunturi

Nagalinga Swamy Basayya Aremallapur

Lokesh Kumar Gupta

Himanshu Varshney

Jafar Sadique Kaviladath

Charls Babu

Vajeed Nimran P A

Supreet Joshi

Samarth S Modi

Harshit Moondra

Shivam Srivastava

Shuaeb Fazeel

Sandeep Jhanwar

Gehesh Edakkuttathil Muhammed

Naveen Kv

William Bright

Rafi Mahammad

Mark Baxter Weaver

A balun includes a first winding which has a first terminal coupled to an input, and a second terminal coupled to a reference potential terminal. The balun includes a second winding magnetically coupled to the first winding. The second winding has a first terminal coupled to a first differential output, a second terminal coupled to a second differential output, and a tap coupled to the reference potential terminal. The balun includes a first capacitor which has a first terminal coupled to the first winding and a second terminal coupled to the second winding. The balun includes a third winding which has a first terminal coupled to the reference potential terminal and a floating second terminal. The balun includes a second capacitor which has a first terminal coupled to the third winding and a second terminal coupled to the second winding.

Balun with improved common mode rejection ratio

In described examples, a circuit includes a multiplexer. The multiplexer receives an input voltage and a calibration signal. An analog-to-digital converter (ADC) is coupled to the multiplexer and generates an output code in response to the calibration signal. A storage circuit is coupled to the ADC and stores the input code representative of the calibration signal at an address corresponding to the output code. The stored input code includes an index value and a coarse value.

Lookup table for non-linear systems

An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.

Multi-bit voltage-to-delay conversion in data converter circuitry

An example sample-and-hold circuit includes a first and second input resistors, each having first and second terminals; first and second transistors coupled in series between the second terminals of the first and second input resistors; and third and fourth input resistors, each having first and second terminals; and third and fourth transistors coupled in series between the second terminals of the third and fourth input resistors. A first capacitor is coupled between the first and second transistors and a second capacitor is coupled between the third and fourth transistors. The control terminals of the first and third transistors are coupled together, and the control terminals of the second and fourth transistors are coupled together.

Current-based track and hold circuit

In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.

Calibration scheme for filling lookup table in an ADC

The disclosure provides a time gain compensation (TGC) circuit. The TGC circuit includes an impedance network. A differential amplifier is coupled to the impedance network. The differential amplifier includes a first input port, a second input port, a first output port and a second output port. A first feedback resistor is coupled between the first input port and the first output port. A second feedback resistor is coupled between the second input port and the second output port. The impedance network provides a fixed impedance to the differential amplifier when a gain of the TGC circuit is changed from a maximum value to a minimum value.

Time gain compensation circuit in an ultrasound receiver

A circuit includes a filter, a first inverter, and a second inverter. The filter is coupled to an input of the first inverter. The second inverter includes an input and an output. The input of the second inverter is coupled to the output of the first inverter. The output of the second inverter is coupled to the input of the first inverter. The filter includes a notch filter and a bandpass filter.

Clock filter with negative resistor circuit

An analog-to-digital converter (ADC) having an input operable to receive an input voltage, V, and an output operable to output a digital code representative of V, the ADC including: a voltage-to-delay circuit having an input and an output, the input of the voltage-to-delay circuit coupled to the input of the ADC; a folding circuit having an input and an output, the input of the folding circuit coupled to the output of the voltage-to-delay circuit; and a time delay-based analog-to-digital converter backend having an input and a digital code output coupled to the output of the ADC, the input of the time delay-based analog-to-digital converter backend coupled to the output of the folding circuit.

Conversion and folding circuit for delay-based analog-to-digital converter system

In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.

Gain and memory error estimation in a pipeline analog to digital converter

A sample-and-hold circuit includes a first input resistor, a first transistor, a first capacitor, a second resistor, and a first current source device. A first current terminal of the first transistor is coupled to the first input resistor. A first terminal of the first capacitor is coupled to the second current terminal of the first transistor at a first output node. A first terminal of the second resistor is coupled to the second terminal of the first transistor at the first output node. The first current source device is coupled the first input resistor and to the first current terminal of the first transistor.

A system has a digital-to-analog converter; a reference signal coupled to the digital-to-analog converter; a differential amplifier for applying gain, and for generating output signals as a function of sampled input signals, the reference signal, digital codes, and the gain applied by the differential amplifier coupled to the digital-to-analog converter; and a multi-bit successive-approximation register for determining the digital codes in successive stages coupled to the differential amplifier; and the gain applied by the differential amplifier is corrected based on previously determined digital codes.

Gain correction for multi-bit successive-approximation register

A circuit includes a filter, a first inverter, and a second inverter. The filter is coupled to an input of the first inverter. The second inverter includes an input and an output. The input of the second inverter is coupled to the output of the first inverter. The output of the second inverter is coupled to the input of the first inverter.

An RF receiver including: a low noise amplifier adapted to be coupled to an antenna and having an output; a bandpass filter coupled to the output of the low noise amplifier and having a voltage signal output, V; a conversion and folding circuit; and an analog-to-digital converter for converting the earlier-arriving or later-arriving delay signals into a digital code representing the voltage signal. The conversion and folding circuit including: a voltage-to-delay converter block, including preamplifiers, for converting the voltage signal into delay signals; and a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals.

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Bengaluru, India

Shagun Dusad