Marvell International Limited

Marvellworld Trade Ltd.

Apple Inc.

Appl Inc.

Shafiq M Jamal

Xiaoyue Wang

Shingo Hatanaka

Francesco Rezzi

Giovanni Cesura

Nicola Ghittori

Hung Sheng Lin

Ovidiu Carnu

Sang Young Youn

Dennis Sinitsky

Ashutosh Verma

Sehat Sutardja

Ahmad Al-Dahle

Tao Shui

Thomas B Cho

Saman Saeedi

Junshi Qiao

Wei Hsin Yao

Hopil Bae

Lawrence Tse

Kingsuk Brahma

Timothy J Donovan

Yonghua Song

Pierte Roo

Taif Ahmed Syed

Chia-Chun Chung

Mir Bahram Ghaderi

Tam Tran

Daniel A Villamizar

Guiseppe De Vita

Stefano Marchesi

Alessandro Pesucci

A finger metal oxide metal capacitor including an outer conducting structure and an inner conducting structure. The outer conducting structure is defined in a plurality of metal layers and a plurality of via layers of an integrated circuit and includes first and second side portions. An inner conducting structure is defined in the plurality of metal layers and the plurality of via layers of the integrated circuit. Each of the outer conducting structure and the inner conducting structure includes respective finger sections extending in the plurality of metal layers. Oxide is arranged between the outer conducting structure and the inner conducting structure.

Finger metal oxide metal capacitor formed in a plurality of metal layers

A method for testing integrated circuit-to-substrate joints that electrically connect an IC to a substrate. An ammeter is coupled to a test node of the driver IC, while the test node is coupled to a current source, and a measured current output of the ammeter is recorded. A voltmeter is coupled to the test node while the test node is coupled to an end node of a group of dummy IC-to-substrate joints that are daisy chained; a first measured voltage output of the voltmeter is then recorded. The IC then couples the test node to another end node of the daisy chained dummy joints, and a second measured voltage output is recorded. A resistance or admittance value for the electrical connection of the IC to the substrate is then computed, using the first and second measured voltage outputs and the measured current output. Other embodiments are also described and claimed.

Testing of integrated circuit to substrate joints

Circuits having corresponding methods and computer-readable media comprise: an amplifier; a crystal port configured to be electrically coupled to a crystal, wherein a first terminal of the crystal port is electrically coupled to an input of the amplifier, and wherein a second terminal of the crystal port is electrically coupled to an output of the amplifier; a first capacitor, wherein a first terminal of the first capacitor is electrically coupled to ground; a second capacitor, wherein a first terminal of the second capacitor is electrically coupled to ground; a first switch configured to selectively electrically couple the input of the amplifier to a second terminal of the first capacitor; and a second switch configured to selectively electrically couple the output of the amplifier to a second terminal of the second capacitor.

Crystal oscillator with low-power mode

A voltage regulator including a first, second, and third capacitances, first switches, and second switches. A first terminal of the first capacitance is connected to a first output. The first output is at a first output voltage. A first terminal of the second capacitance is connected to a second output. The second output is at a second output voltage. The first switches connect a first terminal of the third capacitance to a voltage supply, the first output, or the second output. The second switches connect a second terminal of the third capacitance to a reference terminal, the first output, or the second output. The first and second switches are controlled, based on the first output voltage and the second output voltage, to: adjust voltages across the first, second, and third capacitances; maintain the first output at a first predetermined voltage; and maintain the second output at a second predetermined voltage.

Voltage regulator and method for regulating dual output voltages by selective connection between a voltage supply and multiple capacitances

A resonant element driver circuit includes a NMOS transistor and a PMOS transistor that are configured to drive a resonant element. The resonant element driver circuit includes biasing circuitry that is configured to bias the PMOS transistor. The biasing circuitry receives a reference signal that is used to set the biasing on the PMOS transistor. The resonant element driver further includes mirror circuitry that tracks current flowing through the NMOS and PMOS transistors.

Class-AB XTAL circuit

The present disclosure includes systems and techniques relating to low power current-voltage mixed analog to digital converter (ADC) architecture. In some implementations, an ADC device includes a comparator array configured to receive an input analog voltage signal during a sample phase and a collection of reference voltages during a hold phase, a capacitor configured to receive the input analog voltage signal during the sample phase and to act as a feedback capacitor during the hold phase, an opamp coupled with the capacitor, and a transistor array configured to be powered by the opamp and activated by the comparator array to add or subtract currents to form a residue output voltage signal, which corresponds to the input analog voltage signal, used in analog to digital conversion of the input analog voltage signal.

Low power current-voltage mixed ADC architecture

The present disclosure describes apparatuses and techniques for detection of an external oscillator. In some aspects, an integrated circuit includes an oscillator detector coupled to an external electrical connection. The oscillator detector may include a transistor having a gate coupled to the external electrical connection that is configured to detect a presence of an external oscillator.

External oscillator detector

Systems, methods, and devices are provided to reduce or eliminate mura artifacts on electronic displays. For example, pixels may be programmed to a uniform gray level before all or a substantial number of gates of the pixels are activated. The voltages on some or all source lines that supply the pixels may be measured. A mura artifact may be seen when voltage differences on the source lines are present. As such, operational parameters of the electronic display may be adjusted to reduce or eliminate the mura artifact by reducing the voltage differences.

Systems and methods for calibrating a display to reduce or eliminate mura artifacts

Systems, devices, and methods for using clock detector circuitry to reduce turn-on time of an electronic display, improve image quality, and reduce operations of a host are provided. In one example, a system may include a host configured to transmit a number of signals and a display driver coupled to the host. The number of signals may include a clock signal and data signals. The display driver is configured to drive a display based at least in part on the data signals. The display driver is also configured to be reset upon detection of the clock signal without waiting for a host-issued reset signal. A clock detect circuit configured to detect the clock signal may be configured to transmit an internal reset signal to reset the display driver without a dedicated host-issued reset signal.

Using clock detect circuitry to reduce panel turn-on time

The present disclosure is directed to systems and methods for determining sheet resistance values in a liquid crystal display (LCD) panel. In certain embodiments, a system for determining sheet resistance values in an LCD panel may include a display driver integrated circuit (IC). The display driver IC may include a first switch coupled to a first input/output (I/O) pad and a second I/O pad such that the first I/O pad is configured to couple to a voltage source and the second I/O pad is configured to couple to a current source. The display driver IC may also include a second switch coupled to a third I/O pad and the second I/O pad such that the second switch has substantially the same geometry as the first switch and the third I/O pad is configured to couple to a thin-film transistor (TFT) layer of the display panel.

Systems and methods for measuring sheet resistance

A finger metal oxide metal (MOM) capacitor includes an outer conducting structure defined in a plurality of metal layers and a plurality of via layers of an integrated circuit. First and second side portions include a plurality of first and second finger sections extending in the plurality of metal layers and first and second hole vias connecting the first and second finger sections, respectively. A middle portion connects the first and second side portions. An inner conducting structure is defined in the plurality of metal layers and the plurality of via layers of the integrated circuit. A plurality of 'T'-shaped sections are defined in the plurality of metal layers and third hole vias connecting the plurality of 'T'-shaped sections. Middle portions of the plurality of &#x201c;T&#x201d;-shaped sections extend towards the middle portion and between the first side portion and the second side portion of the outer conducting structure.

Finger metal oxide metal capacitor structures

Better performance can be provided for a display system that has semiconductor microelectronic components such as demultiplexors, gate line and data line drivers, and pixel switches formed on the display substrate, e.g., a glass substrate that constitutes part of an active matrix display panel. A gate source capacitance of a constituent transistor of one of these microelectronic components, e.g., a pixel thin film transistor (TFT) that is part of a particular display element, may be measured using a replica component that emulates the behavior of the component.

Measurement of transistor gate source capacitance on a display system substrate using a replica transistor

A low-dropout converter includes a capacitor and a resistor. The resistor is coupled to the capacitor. The resistor includes a fixed resistor and at least one variable resistor. The capacitor and the resistor determine the location of a zero of the transfer function of the low-dropout converter.

Low-dropout converters with feedback compensation

A display system includes a display panel of pixels, a gate driver and a compensation unit. The gate driver receives a control signal and based on the control signal, generates a gate signal to drive a transistor included in a pixel. The compensation unit measures and compensates for a fall time of the gate driver. The compensation unit includes a replica gate driver, a peak RMS detector, a comparator and a counter. The replica gate driver generates a replica gate signal based on the control signal. The peak RMS detector calculates a peak RMS of the replica gate signal. The comparator compares the peak RMS of the replica gate signal and a reference voltage and generates a comparator value. The counter is controlled by the comparator value to generate a compensation value used to adjust the gate driver and the replica gate driver. Other embodiments are also described and claimed.

Gate driver fall time compensation

A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal.

Growing community of inventors

Gilroy, CA, United States of America

Shafiq M Jamal