International Business Machines Corporation

Globalfoundries Inc.

Nexcis

Shafaat Ahmed

Hariklia Deligianni

Lubomyr Taras Romankiw

Qiang Huang

Kejia Wang

Raman Vaidyanathan

Qiang Fang

Dinesh R Koli

Dario Leonardo Goldfarb

Jiehui Shu

Stephen Mark Rossnagel

Gustavo Alejandro Stolovitzky

Stefan Harrer

Stanislav Polonsky

Hongbo Peng

Xiaoyan Shao

Murshed Chowdhury

Zhiguo Sun

Joyeeta Nag

Aritra Dasgupta

Benjamin G Moser

Shahrukh Akbar Khan

Mohammad Hasanuzzaman

Changhong Wu

Ali Afzali-Ardakani

Haigou Huang

Vimal Kumar Kamineni

Glenn John Martyna

Binquan Luan

Atsushi Ogino

Wei-Tsu Tseng

Kathleen B Reuter

Vishal Chhabra

Salvador Jaime

Sukjay Chey

Sadanand Vinayak Despande

Philippe De Gasquet

Ali Afzali-Azdakani

A chalcogen-resistant material including at least one of a conductive elongated nanostructure layer and a high work function material layer is deposited on a transition metal layer on a substrate. A semiconductor chalcogenide material layer is deposited over the chalcogen-resistant material. The conductive elongated nanostructures, if present, can reduce contact resistance by providing direct electrically conductive paths from the transition metal layer through the chalcogen-resistant material and to the semiconductor chalcogenide material. The high work function material layer, if present, can reduce contact resistance by blocking chalcogenization of the transition metal in the transition metal layer. Reduction of the contact resistance can enhance efficiency of a solar cell including the chalcogenide semiconductor material.

Ohmic contact of thin film solar cell

Techniques for electrodepositing selenium (Se)-containing films are provided. In one aspect, a method of preparing a Se electroplating solution is provided. The method includes the following steps. The solution is formed from a mixture of selenium oxide; an acid selected from the group consisting of alkane sulfonic acid, alkene sulfonic acid, aryl sulfonic acid, heterocyclic sulfonic acid, aromatic sulfonic acid and perchloric acid; and a solvent. A pH of the solution is then adjusted to from about 2.0 to about 3.0. The pH of the solution can be adjusted to from about 2.0 to about 3.0 by adding a base (e.g., sodium hydroxide) to the solution. A Se electroplating solution, an electroplating method and a method for fabricating a photovoltaic device are also provided.

Method and chemistry for selenium electrodeposition

The present disclosure relates to semiconductor structures and, more particularly, to a cobalt plated via integration scheme and methods of manufacture. The structure includes: a via structure composed of cobalt material; and a wiring structure above the via structure. The wiring structure is lined with a barrier liner and the cobalt material and filled with conductive material.

Cobalt plated via integration scheme

The disclosure relates to a method of forming a Co contact module, the method including depositing a liner layer on a trench block, partially plating the lined trenches with Co as a first metal such that the resulting Co layer has a top surface below an opening top surface of a shallowest trench, depositing a second metal on the Co layer and exposed surfaces of the liner layer, planarizing the second metal layer, and etching the second metal layer and portions of the liner layer. The disclosure also relates to a Co contact module formed by the noted method.

Method of forming cobalt contact module and cobalt contact module formed thereby

A method of forming hybrid Co and Cu CA/CB contacts and the resulting device are provided. Embodiments include forming a forming a plurality of trenches through an ILD down to a substrate; forming a first metal liner on side and bottom surfaces of each trench and over the ILD; annealing the first metal liner; forming a second metal liner over the first metal liner; forming a first plating layer over a portion of the second metal liner in each trench; forming a second plating layer over the second metal liner and first plating layer in a remaining portion of each trench, the first and second plating layers being different materials; and planarizing the second plating layer and the second and first metal liners down to the ILD.

Method to prevent cobalt recess

The present disclosure relates to semiconductor structures and, more particularly, to a corrosion and/or etch protection layer for contacts and interconnect metallization integration structures and methods of manufacture. The structure includes a metallization structure formed within a trench of a substrate and a layer of cobalt phosphorous (CoP) on the metallization structure. The CoP layer is structured to prevent metal migration from the metallization structure and corrosion of the metallization structure during etching processes.

Corrosion and/or etch protection layer for contacts and interconnect metallization integration

A method includes providing a semiconductor substrate having horizontal and vertical scribe lines thereon defining semiconductor areas for printed circuits and/or semiconductor devices, and forming a metallic structure on the semiconductor substrate to serve as a bus bar for the printed circuits and/or semiconductor devices. A semiconductor structure is realized with the method, the semiconductor structure including a semiconductor substrate having horizontal and vertical scribe lines thereon defining semiconductor areas for printed circuits and/or semiconductor devices, a metallic structure on the semiconductor substrate serving as a bus bar for the printed circuits and/or semiconductor devices, and printed circuits and/or semiconductor devices in the semiconductor areas.

Structure and method of conductive bus bar for resistive seed substrate plating

One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: forming a first work function metal over a set of fins having at least a first fin and a second fin; implanting the first work function metal with a first species; removing the implanted first work function metal from over the first fin such that a remaining portion of the implanted first work function metal remains over the second fin; forming a second work function metal over the set of fins including over the remaining portion of the implanted first work function metal; implanting the second work function metal with a second species; and forming a metal over the implanted second work function metal over the set of fins thereby forming the gate stack.

Gate stack for integrated circuit structure and method of forming same

The invention relates to manufacturing a I-III-VI compound in the form of a thin film for use in photovoltaics, including the steps of: a) electrodepositing a thin-film structure, consisting of I and/or III elements, onto the surface of an electrode that forms a substrate (SUB); and b) incorporating at least one VI element into the structure so as to obtain the I-III-VI compound. According to the invention, the electrodeposition step comprises checking that the uniformity of the thickness of the thin film varies by no more than 3% over the entire surface of the substrate receiving the deposition.

Checking the stoichiometry of I-III-VI layers for use in photovoltaic using improved electrolysis conditions

A method of forming a finFET structure having an ion implanted intermediate region next to the channel region of a finFET gate. The intermediate region is formed in a manner to reduce or eliminate migration of the dopant to undoped regions of the finFET thus forming abrupt finFET junction.

Formation of finFET junction

Photovoltaic devices and methods for preparing a p-type semiconductor generally include electroplating a layer of gallium or a gallium alloy onto a conductive layer by contacting the conductive layer with a plating bath free of complexing agents including a gallium salt, methane sulfonic acid or sodium sulfate and an organic additive comprising at least one nitrogen atom and/or at least one sulfur atom, and a solvent; adjusting a pH of the solution to be less than 2.6 or greater than 12.6. The photovoltaic device includes an impurity in the p-type semiconductor layer selected from the group consisting of arsenic, antimony, bismuth, and mixtures thereof. Various photovoltaic precursor layers for forming CIS, CGS and CIGS p-type semiconductor structures can be formed by electroplating the gallium or gallium alloys in this manner. Also disclosed are processes for forming a thermal interface of gallium or a gallium alloy.

Electrodeposition methods of gallium and gallium alloy films and related photovoltaic structures

In one aspect, a method for fabricating a thin film solar cell includes the following steps. A first absorber material is deposited as a layer A on a substrate while applying pressure to the substrate/layer A. A second absorber material is deposited as a layer B on layer A while applying pressure to the substrate/layer B. A third absorber material is deposited as a layer C on layer B while applying pressure to the substrate/layer C. A fourth absorber material is deposited as a layer D on layer C while applying pressure to the substrate/layer D. The first absorber material comprises copper, the second absorber material comprises indium, the third absorber material comprises gallium, and the fourth absorber material comprises one or more of sulfur and selenium, and wherein by way of performing the steps of claima chalcogenide absorber layer is formed on the substrate.

Pressure transfer process for thin film solar cell fabrication

Techniques for electrodepositing zinc (Zn)-containing films are provided. In one aspect, a method of preparing a Zn electroplating solution is provided. The method includes the following steps. The solution is formed from a mixture of at least one zinc salt, a sulfonic acid and a solvent. The sulfonic acid is quenched with a base. A pH of the solution is adjusted to be either less than about 3.5 or greater than about 8.0. The pH of the solution can be adjusted by adding additional sulfonic acid to the solution to adjust the pH of the solution to be less than about 3.5 or by adding a second base to the solution to adjust the pH of the solution to be greater than about 8.0. A Zn electroplating solution and an electroplating method are also provided.

Zinc thin films plating chemistry and methods

Techniques for using electrodeposition to form absorber layers in diodes (e.g., solar cells) are provided. In one aspect, a method for fabricating a diode is provided. The method includes the following steps. A substrate is provided. A backside electrode is formed on the substrate. One or more layers are electrodeposited on the backside electrode, wherein at least one of the layers comprises copper, at least one of the layers comprises zinc and at least one of the layers comprises tin. The layers are annealed in an environment containing a sulfur source to form a p-type CZTS absorber layer on the backside electrode. An n-type semiconductor layer is formed on the CZTS absorber layer. A transparent conductive layer is formed on the n-type semiconductor layer. A diode is also provided.

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Yorktown Heights, NY, United States of America

Shafaat Ahmed